HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 674

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 20 Power-Down State
When the WDT is used as a watchdog timer (WT/IT = 1), the TME bit must be cleared to 0 before
setting SSBY. Also, when setting TME to 1, SSBY should be cleared to 0.
Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software
standby mode.
20.4.2
Software standby mode can be exited by input of an external interrupt at the NMI, IRQ
IRQ
Exit by Interrupt: When an NMI, IRQ
clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0
in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and
interrupt exception handling begins. Software standby mode is not exited if the interrupt enable
bits of interrupts IRQ
CPU.
Exit by RES
supplied immediately to the entire chip. The RES signal must be held low long enough for the
clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling.
Exit by STBY
20.4.3
Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows.
Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to
stabilize) is at least 7 ms. Table 20.3 indicates the waiting times that are selected by STS2 to
STS0, DIV1, and DIV0 settings at various system clock frequencies. Refer to the clock frequency
and the waiting time in which it takes for the clock to settle, as shown in table 20.3.
External Clock: Set bits STS2 to STS0, Bits DIV0, and DIV1 so that the waiting time is 100 s
or more.
Rev. 3.00 Sep 27, 2006 page 646 of 872
REJ09B0325-0300
2
pin, or by input at the RES or STBY pin.
RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are
RES
RES
STBY
STBY
STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.
Exit from Software Standby Mode
Selection of Waiting Time for Exit from Software Standby Mode
0
, IRQ
1
, and IRQ
2
are cleared to 0, or if these interrupts are masked in the
0
, IRQ
1
, or IRQ
2
interrupt request signal is received, the
0
, IRQ
1
, or