HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 459
![IC H8 MCU FLASH 128K 100QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
HD64F3048BF25
Manufacturer Part Number
HD64F3048BF25
Description
IC H8 MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.DF3048BF25V.pdf
(903 pages)
Specifications of HD64F3048BF25
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3048BF25
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F3048BF25V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 459 of 903
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11.3
11.3.1
When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output
is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.
When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit
contents are transferred to PADR or PBDR to update the output values.
Figure 11.2 illustrates the TPC output operation. Table 11.3 summarizes the TPC operating
conditions.
Table 11.3 TPC Operating Conditions
NDER
0
1
Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and
NDRB before the next compare match. For information on non-overlapping operation, see section
11.3.4, Non-Overlapping TPC Output.
TPC output pin
Operation
Overview
DDR
0
1
0
1
DDR
Q
Pin Function
Generic input port
Generic output port
Generic input port (but the DR bit is a read-only bit, and when compare
match occurs, the NDR bit value is transferred to the DR bit)
TPC pulse output
Figure 11.2 TPC Output Operation
Q
NDER
Q
DR
C
Output trigger signal
Section 11 Programmable Timing Pattern Controller
D
Rev. 3.00 Sep 27, 2006 page 431 of 872
Q
NDR
D
REJ09B0325-0300
Internal
data bus
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