XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 120

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
B
IT
N
UMBER
7
6
5
SLC 96 Enable
MOS ABORT Enable
Receive FCS Verification
Enable
B
IT
N
AME
B
IT
R/W
R/W
R/W
T
YPE
SLC 96 Enable:
This READ/WRITE bit-field permits the user to enable SLC 96
data link transmission in SLC 96 framing mode. In ESF framing
mode, this READ/WRITE bit-field allows Facility Data Link of the
framer to transmit and receive SLC 96-like message.
When this bit is set to zero:
In SLC 96 framing mode, the SLC 96 data link transmission is
disabled. The framer transmits Terminal Framing bits as in SF
framing mode. The Signaling Framing bits are forced to ones.
In ESF framing mode, Facility Data Link of the framer is config-
ured to transmit and receive regular data link message.
When this bit is set to one:
In SLC 96 framing mode, the SLC 96 data link transmission is
enabled. The framer transmits Terminal Framing bits as in SF
framing mode. The Signaling Framing bits are transmitted and
received in SLC 96 data link format.
In ESF framing mode, Facility Data Link of the framer is config-
ured to transmit and receive SLC 96-like message.
MOS ABORT Enable:
This READ/WRITE bit-field enables and disables the Transmit
LAPD Controller of the framer to automatically insert an ABORT
sequence anytime it transitions from the Message Oriented Sig-
naling (MOS) mode to the Bit Oriented Signaling (BOS) mode.
When this bit is set to zero:
The Transmit LAPD Controller inserts an MOS ABORT
sequence to the data link message when the framer transitions
from MOS to BOS.
When this bit is set to one:
The Transmit LAPD Controller does not insert an MOS ABORT
sequence to the data link message when the framer transitions
from MOS to BOS.
Receive FCS Verification Enable:
This READ/WRITE bit-field enables and disables the Receive
LAPD Controller of the framer to compute and verify the Frame
Check Sequence (FCS) value in the incoming LAPD message.
When this bit is set to zero:
The Receive LAPD Controller computes and verifies the Frame
Check Sequence (FCS) of each MOS message.
When this bit is set to one:
The Receive LAPD Controller does not compute and verify the
Frame Check Sequence (FCS) of each MOS message.
100
B
IT
D
ESCRIPTION
REV. 1.0.1