XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 410

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
If Loss of Signal condition is present in the incoming E1 frame, the XRT84L38 framer can generate a Receive
Loss of Signal interrupt associated with the setting of Receive Loss of Signal bit of the Alarm and Error Status
Register to one.
To enable the Receive Loss of Signal interrupt, the Receive Loss of Signal Interrupt Enable bit of the Alarm and
Error Interrupt Enable Register (AEIER) has to be set to one. In addition, the Alarm and Error Interrupt Enable
bit of the Block Interrupt Enable Register (BIER) needs to be one.
The table below shows configurations of the Receive Loss of Signal Interrupt Enable bit of the Alarm and Error
Interrupt Enable Register (AEIER).
ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H)
The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H)
When these interrupt enable bits are set and one or more Loss of Signals are present in the incoming E1
frame, the XRT84L38 framer will declare Receive Loss of Signal by doing the following:
•
Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status
indicators.
The table below shows the Receive Loss of Signal status bits of the Alarm and Error Status Register.
ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H)
13.0 DS1 HDLC CONTROLLER BLOCK
13.1
13.1.1
N
N
N
·Set the Receive Loss of Signal bit of the Alarm and Error Status Register to one indicating there is one or
more Loss of Signals. This status indicator is valid until the Framer Interrupt Status Register is read.
UMBER
UMBER
UMBER
B
B
B
4
1
4
IT
IT
IT
DS1 Transmit HDLC Controller Block
Description of the DS1 Transmit HDLC Controller Block
Receive Loss of
Alarm and Error
Interrupt Enable
Receive Loss of
Signal Interrupt
Signal State
B
B
B
Enable
IT
IT
IT
N
N
N
AME
AME
AME
B
B
B
RUR /
IT
IT
IT
R/W
R/W
WC
T
T
T
YPE
YPE
YPE
0 - The Receive Loss of Signal interrupt is disabled. Occurrence of Loss of
Signals will not generate an interrupt.
1 - The Receive Loss of Signal interrupt is enabled. Occurrence of Loss of
Signals will generate an interrupt.
0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is disabled.
1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is enabled.
0 - There is no change of Loss of Signal state in the incoming E1 payload
data.
1 - There is change of Loss of Signal state in the incoming E1 payload
data.
390
B
B
B
IT
IT
IT
D
D
D
ESCRIPTION
ESCRIPTION
ESCRIPTION
REV. 1.0.1