XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 205

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
Figure 24
that connect the Transmit Payload Data Input Interface block to the local Terminal Equipment with the Transmit
Serial clock being the timing source of transmit section.
By setting the Transmit Timing Source [1:0] bits of the Clock Select Register (CSR) to 10, the OSCCLK Driven
Divided clock is configured to be the timing source for the Transmit section of the framer. A free-running clock
should apply to the OSCCLK input pin with frequencies of 12.352MHz, 24.704MHz and 49.408MHz depending
on the setting of OSCCLK Frequency Select [1:0] bits of the Clock Select Register (CSR).
The free-running OSCCLK is divided inside the XRT84L38 and routed to all eight framers. This OSCCLK Driven
Divided Clock has to be 12.352MHz in frequency. When these bits are set to 00, the framer will internally divide
the incoming OSCCLK by one. Therefore, the external oscillator clock applied to the OSCCLK pin should be
12.352MHz. When these bits are set to 01, the framer will internally divide the incoming OSCCLK by two.
Therefore, the external oscillator clock applied to the OSCCLK pin should be 24.704MHz. When these bits are
set to 10, the framer will internally divide the incoming OSCCLK by four. Therefore, the external oscillator clock
applied to the OSCCLK pin should be 49.408MHz.
The following table shows configurations of the OSCCLK Frequency Select [1:0] bits of the Clock Select Register.
F
TO THE LOCAL
T
4.1.2.2
RANSMIT
IGURE
TxTSb[1]/TxFrTD
TxTSb[0]/TxSig
TxSerClk (INV)
TxSync(input)
24. W
TxTSb[4:0]
TxTSb[4:0]
S
shows waveforms of the signals (TxSerClk_n, TxSer_n, TxSync_n, TxTSClk_n and TxTSb[4:0]_n)
TxSerClk
ECTION
TxTSClk
TxTSClk
Connect the Transmit Payload Data Input Interface block to the Local Terminal Equipment
if the Transmit Timing Source = OSCCLK
TxSer
AVEFORMS OF THE SIGNALS THAT CONNECT THE
T
ERMINAL
F
E
Timeslot #0
c1 c2 c3 c4 c5
1
QUIPMENT WITH THE
2
Timeslot 0
Input Data
3
4
A B
5
6
C
7
D
8
T
RANSMIT
c1 c2 c3 c4 c5
Timeslot #5
Timeslot 5
Input Data
185
S
A B
ERIAL CLOCK BEING THE
T
C
RANSMIT
D
c1 c2 c3 c4 c5
1
Timeslot #6
2
Timeslot 6
Input Data
3
P
4
AYLOAD
A B
5
6
C
7
D
8
D
T
OCTAL T1/E1/J1 FRAMER
ATA
IMING
I
NPUT
c1 c2 c3 c4 c5
S
Timeslot #23
OURCE OF THE
Timeslot 23
Input Data
I
NTERFACE BLOCK
XRT84L38
A B
C
D
F