XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 272

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The following
TxTSb[4:0]_n) that connecting the Transmit Payload Data Input Interface block to the local Terminal Equipment
with the Transmit Serial clock being the timing source of transmit section.
By setting the Transmit Timing Source [1:0] bits of the Clock Select Register (CSR) to 10, the OSCCLK Driven
Divided clock is configured to be the timing source for the Transmit section of the framer. A free-running clock
should apply to the OSCCLK input pin with frequencies of 16.384MHz, 32.768MHz and 65.536MHz depending
on the setting of OSCCLK Frequency Select [1:0] bits of the Clock Select Register (CSR).
The free-running OSCCLK is divided inside the XRT84L38 and routed to all eight framers. This OSCCLK
Driven Divided Clock has to be 16.384MHz in frequency. When these bits are set to 00, the framer will
internally divide the incoming OSCCLK by one. Therefore, the external oscillator clock applied to the OSCCLK
pin should be 16.384MHz. When these bits are set to 01, the framer will internally divide the incoming
OSCCLK by two. Therefore, the external oscillator clock applied to the OSCCLK pin should be 32.768MHz.
When these bits are set to 10, the framer will internally divide the incoming OSCCLK by four. Therefore, the
external oscillator clock applied to the OSCCLK pin should be 65.536MHz.
F
TO THE LOCAL
MIT
6.1.2.2
IGURE
S
TxChn[1]/TxFrTD
ECTION
TxSync(output)
TxChn[0]/TxSig
TxSerClk (INV)
TxSync(input)
64. W
TxChn[4:0]
TxTSb[4:0]
TxSerClk
TxChClk
TxTSClk
TxSer
Connect the Transmit Payload Data Input Interface block to the Local Terminal Equipment
if the Transmit Timing Source = OSCCLK
AVEFORMS OF THE SIGNALS THAT CONNECT THE
Figure 64
T
ERMINAL
F
Timeslot #0
E
c1 c2 c3 c4 c5
1
shows waveforms of the signals (TxSerClk_n, TxSer_n, TxSync_n, TxTSClk_n and
QUIPMENT WITH THE
2
Timeslot 0
Input Data
3
4
A B
5
6
C
7
D
8
T
RANSMIT
c1 c2 c3 c4 c5
Timeslot #5
Timeslot 5
Input Data
252
S
ERIAL CLOCK BEING THE TIMING SOURCE OF THE
A B
T
RANSMIT
C
D
c1 c2 c3 c4 c5
1
Timeslot #6
2
Timeslot 6
Input Data
3
P
AYLOAD
4
A B
5
6
C
7
D
D
8
ATA
I
NPUT
c1 c2 c3 c4 c5
Timeslot #23
I
NTERFACE
Timeslot 23
Input Data
A B
REV. 1.0.1
C
B
T
D
RANS
LOCK
F
-