XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 124

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
Slip Buffer Control Register (SBCR) (Indirect Address = 0xn0H, 0x16H)
Transmit Slip
B
B
IT
IT
Buffer is
B
FIFO
N
6 - 0
R/W
N
6 - 5
IT
UMBER
0
UMBER
7
7
Receive Data Link Byte
Count [6:0]
Transmit Slip Buffer is
FIFO
Reserved
B
R/W
IT
0
6
B
B
Reserved
IT
IT
N
N
AME
AME
B
R/W
IT
0
5
B
B
IT
IT
R/W
R/W
Signaling
T
T
Freeze
YPE
Force
YPE
B
R/W
IT
0
4
Receive Data Link Byte Count [6:0]:
These READ/WRITE bit-fields hold the length of the MOS mes-
sage received or the number of repetitions of BOS message
received. The user should program these bit-fields to equal the
length of the MOS message in bytes or the number of repetitions
of BOS message.
The LAPD controller will load the value of these bits from the
Receive Data Link Byte Count register and use it as its internal
counter at the beginning of each transfer. After the entire MOS
message is received or x number of repetitions of BOS message
is received, the LAPD controller will generate the Receive End of
Transfer (RxEOT) interrupt.
Each Receive Data Link Buffer is 96-bytes wide.
N
Slip Buffer is FIFO:
This READ/WRITE bit-field allows the user to determine function
of the buffer when TxLineClk_n and TxSerClk_n are synchro-
nized with each other.
When this bit is 0:
The buffer acts as slip buffer if enabled by the Slip Buffer Enable
bit [1:0].
When this bit is 1:
The buffer acts as FIFO.
OTE
104
: In the case of BOS messaging, these bit-fields cannot be
Signaling
set to zero. Otherwise, no Receive End of Transfer
(RxEOT) interrupt will be generated.
Freeze
Enable
B
R/W
IT
0
3
Synchroniza-
tion Direction
Slip Buffer
Receive
B
B
B
R/W
IT
IT
IT
0
D
D
2
ESCRIPTION
ESCRIPTION
Slip Buffer Enable Bit [1:0]
B
R/W
IT
0
1
REV. 1.0.1
B
R/W
IT
0
0