XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 376

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The E bit Source Select bit of the Synchronization MUX Register (SMR) controls from where to input E bits into
the framer. The table below shows configurations of the E bit Source Select bit of the Synchronization MUX
Register (SMR).
SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H)
11.3
The XRT84L38 T1/J1/E1 Octal Framer provides individual control of each of the thirty two DS0 channels. The
user can apply data and signaling conditioning to raw E1 payload data coming from the Terminal Equipment on
a per-channel basis.
The XRT84L38 framer can apply the following changes to raw E1 PCM data coming from the Terminal
Equipment on a per-channel basis:
•
•
•
•
•
Configuration of the XRT84L38 framer to apply the above-mentioned changes to raw E1 PCM data are
controlled by the Transmit Data Conditioning Select [3:0] bits of the Transmit Channel Control Register (TCCR)
of each DS0 channel.
The XRT84L38 framer can also replace the incoming raw E1 PCM data from the Terminal Equipment with pre-
defined or user-defined codes. The XRT84L38 supports the following conditioning substitutions:
•
•
•
•
•
•
•
•
N
All 8 bits of the input PCM data are inverted
The even bits of the input PCM data are inverted
The odd bits of the input PCM data are inverted
The MSB of the input PCM data is inverted
All input PCM data except the MSB are inverted
BUSY code - an octet with hexadecimal value of 0x7F
BUSY_TS code - an octet of pattern "111xxxxx" where "xxxxx" represents the timeslot number
VACANT code - an octet with hexadecimal value of 0xFF
A-law Digital Milliwatt code
u-law Digital Milliwatt code
IDLE code - an octet defined by the value stored in the User IDLE Code Register (UCR)
MOOF code - MUX-Out-Of-Frame code with hexadecimal value of 0x1A
PRBS code - an octet generated by the Pseudo-Random Bit Sequence (PRBS) Generator block of the
framer
UMBER
B
7-6
IT
How to Configure the Framer to Apply Data and Signaling Conditioning to E1 Payload Data on a
Per-Channel Basis
E bit Source Select
B
IT
N
AME
B
IT
R/W
T
YPE
These READ/WRITE bit-fields permits the user to determine where the E
bits should be inserted and what the E bits should be.
00 - The E bits are generated and inserted by the framer internally.
01 - The E bits are forced to be "0" and are inserted by the framer inter-
nally.
10 - The E bits are forced to be "1" and are inserted by the framer inter-
nally.
11 - Source of the E bits is HDLC controller of the framer. The E bits are
used to carry data link messages.
356
B
IT
D
ESCRIPTION
REV. 1.0.1