XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 247

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
Payload and signaling data of Channel 0-3 are multiplexed onto the Receive Serial Data pin of Channel 0.
Payload and signaling data of Channel 4-7 are multiplexed onto the Receive Serial Data pin of Channel 4. The
Receive Single-frame Synchronization signal of Channel 0 pulses HIGH at the beginning of the frame with data
from Channel 0-3 multiplexed together. The Receive Single-frame Synchronization signal of Channel 4 pulses
HIGH at the beginning of the frame with data from Channel 4-7 multiplexed together.
The table below summaries the clock frequencies of RxSerClk_n input when the framer is operating in
multiplexed High-speed Back-plane mode.
RECEIVE MULTIPLEX ENABLE BIT = 1
When the frame is running at High-speed Back-plane Interface mode other than the 1.544Mbit/s data rate, the
Receive Single-frame Synchronization signal could pulse HIGH or LOW indicating boundaries of DS1 frames.
The Receive Synchronization Pulse Low bit of the Receive Interface Control Register (TICR) determines
whether the Receive Single-frame Synchronization signal is HIGH active or LOW active.
The table below shows configurations of the Receive Synchronization Pulse LOW bit of the Receive Interface
Control Register (RICR).
RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0xn0H, 0x22H)
Throughout the discussion of this datasheet, we assume that the Receive Single-frame Synchronization signal
pulses HIGH unless stated otherwise.
The following sections discuss details of how to operate the framer in different Back-plane interface speed
mode and how to connect the Receive Payload Data Output Interface block to the local Terminal Equipment.
When the Receive Multiplex Enable bit is set to zero and the Receive Interface Mode Select [1:0] bits are set to
01, the Receive Back-plane interface of framer is running at a data rate of 2.048Mbit/s.
The interface consists of the following pins:
•
•
•
•
5.1.3.1
N
Data input (RxSer_n)
Receive Serial Clock Input signal (RxSerClk_n)
Receive Single-frame Synchronization Input signal (RxSync_n)
Receive Input Clock (RxInClk_n)
R
UMBER
ECEIVE
B
3
IT
S
ELECT
I
NTERFACE
Synchronization
0
0
1
1
T1 Receive Input Interface - MVIP 2.048 MHz
Pulse LOW
B
B
Receive
IT
IT
1
N
AME
M
ODE
R
B
ECEIVE
IT
R/W
T
YPE
S
ELECT
I
NTERFACE
0 - The Receive Single-frame Synchronization signal will pulse HIGH indicat-
ing the beginning of a DS1 frame when the High-speed Back-plane Interface
is running at a mode other than the 1.544Mbit/s.
1 - The Receive Single-frame Synchronization signal will pulse LOW indicat-
ing the beginning of a DS1 frame when the High-speed Back-plane Interface
is running at a mode other than the 1.544Mbit/s.
0
1
0
1
B
IT
0
M
ODE
227
B
Bit-multiplexed 16.384Mbit/s
ACK
Multiplexed 12.352Mbit/s
HMVIP 16.384Mbit/s
H.100 16.384Mbit/s
-
PLANE
R
B
I
NTERFACE
ATE
IT
D
ESCRIPTION
D
ATA
OCTAL T1/E1/J1 FRAMER
12.352 MHz
16.384 MHz
16.384 MHz
16.384 MHz
R
X
S
XRT84L38
ER
C
LK