XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 57

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
The Microprocessor Interface block within the Framer is very flexible and provides the following options:
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The Framer Microprocessor Interface permits the user to interface it to a µC/µP over an 8-bit wide bi-directional
data bus. In general, interfacing the Framer to an 8-bit µC/µP is quite straight-forward. This is because most of
the registers, within the Framer, are 8-bits wide. In this mode, the µC/µP can read or write data into both even
and odd numbered addresses within the Framer address space.
Example:
Consider that an 8-bit µC/µP needs to read in the PMON LCV Event Count Register. In order to accomplish
this task, the 8-bit µC/µP needs to read in the contents of PMON LCV Event Count Register - MSB (located at
Address = 0x50) and the contents of the PMON LCV Event Count Register - LSB (located at Address = 0x51).
These two eight-bit registers when concatenated together make up the PMON LCV Event Count Register.
If the 8-bit µC/µP reads in the PMON LCV Event Count-LSB register first, then the entire PMON LCV Event
Count register will be reset to 0x0000. As a consequence, if the 8-bit µC/µP attempts to read in the PMON LCV
Event Count-MSB register in the very next read cycle, it will read in the value 0x00.
The Microprocessor Interface block supports data transfer between the Framer and the µC/µP (e.g., Read and
Write operations) via the Programmed I/O and the Burst Modes.
Programmed I/O is basically a handshaking type of asynchronous bus access, which provides relatively slow
single read and write data transfers. The Microprocessor must supply an address value to the Address Bus
input pins A[6:0] with each read and write cycle. Because of the Indirect Addressing scheme each PIO reads
and write access requires two accesses, as illustrated below.
In the first access, the Microprocessor is specifying two things:
As a slave, the E1 is the target of access generated by a bus master, the CPU. Slave accesses are accepted by
the slave control state machine, then passed to related functional logic. Address is buffered and decoded to
address relevant destination. Data is also latch in both write and read directions. PIO operations are enabled by
the Chip Select (CS) input signal. Framer PIO interface supports pipelined (buffered) writes to increase bus
throughput. All internal registers and accessible memory are addressable through 6 bits of address bus.
Programmed I/O is the conventional manner in which a microprocessor exchanges data with a peripheral
device. However, it is also the slowest method of data exchange between the Framer and the µC/µP.
If the Framer is interfaced to an Intel-type µC/µP (e.g., the 80x86 family, etc.), then it should be configured to
operate in the Intel mode.
Whenever an Intel-type µC/µP wishes to read the contents of a register or some location within the Receive
LAPD Message buffer or the Receive OAM Cell Buffer, within the Framer, it should do the following.
1. Which of the four framer register sets it intends to access.
2. Which group of registers within the selected framer’s register sets, the Microprocessor wants to access.
1. Place the address of the target register or buffer location, within the Framer, on the Address Bus input pins
1.3.1
1.3.2
1.3.2.1
1.3.2.2
1.3.2.2.1
1.3.2.2.1.1
Interface the Framer to a µC/µP over an 8-bit wide bi-directional data bus.
Interface the Framer to an Intel-type or Motorola-type µC/µP.
Transfer data (between the Framer IC and the µC/µP) via the Programmed I/O or Burst Mode
A[6:0].
Interfacing the Framer to the Microprocessor over an 8 bit wide bi-directional Data Bus
Data Access Modes
Programmed I/O
Data Access using Programmed I/O
Intel Mode Programmed I/O Access
Intel Mode Read Cycle
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OCTAL T1/E1/J1 FRAMER
XRT84L38