XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 304

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The following
RxTSb[4:0]_n) which connecting the Receive Payload Data Output Interface block to the local Terminal
Equipment when the Slip Buffer is enabled.
By setting the Slip Buffer Enable [1:0] bits of the Slip Buffer Control Register to 10, the framer puts the Elastic
Buffer into FIFO mode. Receive Framer Module routes the Receive Payload Data through the First-In-First-Out
storage to the Receive Payload Data Output Interface. The XRT84L38 device uses the Recovered Receive
Line Clock internally to clock in the Receive Payload Data into the FIFO. The Terminal Equipment should
provide an external 2.048MHz clock to the Receive Serial Clock input pin to latch data out from the FIFO.
It is the responsibility of the user to phase lock the input Receive Serial Clock to the Recovered Receive Line
Clock to avoid either over-run or under-run of the FIFO. The latency between writing a bit into the FIFO and
reading the same bit from it (READ and WRITE latency) is actually depth of the FIFO, which is maintained in a
programmable fashion controlled by the FIFO Latency Register (FIFOLR). The largest possible depth of the
FIFO is thirty-two bytes or one E1 frame. The default depth of the FIFO when XRT84L38 first powered up is
four bytes. The table below shows the FIFO Latency Register.
FIFO LATENCY REGISTER (FIFOL) (INDIRECT ADDRESS = 0XN0H, 0X17H)
In this mode, the Receive Single-Frame Synchronization signal can be either input or output depending on the
settings of the Slip Buffer Receive Synchronization Direction bit of the Slip Buffer Control Register. When the
Slip Buffer Receive Synchronization Direction bit is set to 0, the Receive Single-Frame Synchronization signal
(RxSync_n) is an. When the Slip Buffer Receive Synchronization Direction bit is set to 1,the Receive Single-
Frame Synchronization signal (RxSync_n) is an input.
F
BLOCK TO THE LOCAL
6.2.2.3
N
IGURE
UMBER
B
4-0
RxChn[1]/RxFrTD
RxChn[2]/RxChn
IT
RxChn[0]/RxSig
RxSync(output)
RxSync(input)
84. W
RxChn[4:0]
RxSerClk
RxChClk
RxChClk
FIFO Latency
RxSer
Connect the Receive Payload Data Output Interface block to the Local Terminal
Equipment if the Slip Buffer is configured as FIFO
B
Figure 84
AVEFORMS OF THE
IT
N
AME
T
ERMINAL
c1 c2 c3 c4 c5
shows waveforms of the signals (RxSerClk_n, RxSer_n, RxSync_n, RxTSClk_n and
B
Timeslot #0
Timeslot 0
IT
R/W
T
E
YPE
S
QUIPMENT WHEN THE
A B
IGNALS THAT
C
These bits determine depth of the FIFO in terms of bytes. The largest possible
value is thirty-two bytes or one E1 frame.
D
C
c1 c2 c3 c4 c5
ONNECT THE
Timeslot #5
Timeslot 5
284
S
LIP
A B
B
UFFER IS
R
C
ECEIVE
D
c1 c2 c3 c4 c5
1
B
IT
2
Timeslot #6
Timeslot 6
Input Data
E
D
3
P
NABLED
ESCRIPTION
AYLOAD
4
A B
5
6
C
7
D
D
8
ATA
O
UTPUT
c1 c2 c3 c4 c5
Timeslot #16
Timeslot 16
Input Data
I
NTERFACE
A B
REV. 1.0.1
C
D