XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 208

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
Figure 26
that connect the Transmit Payload Data Input Interface block to the local Terminal Equipment with the OSCCLK
Driven Divided clock as the timing source of transmit section.
If the Transmit Timing Source [1:0] bits of the Clock Select Register are set to 00 or 11, the Recovered Receive
Line Clock is configured to be the timing source for the Transmit section of the framer. This is also known as the
Loop-timing mode.
If the Clock Loss Detection Enable bit of the Clock Select Register is set to one, and if the Recovered Receive
Line Clock from the LIU is lost, the framer will automatically begin to use the OSCCLK Driven Divided clock as
transmit timing source until the LIU is able to regain clock recovery.
F
TO THE LOCAL
T
4.1.2.3
RANSMIT
IGURE
TxTSb[1]/TxFrTD
TxTSb[0]/TxSig
TxSync(output)
TxTSb[0]/TxSig
TxSerClk (INV)
26. W
TxTSb[4:0]
S
TxSerClk
shows waveforms of the signals (TxSerClk_n, TxSer_n, TxSync_n, TxTSClk_n and TxTSb[4:0]_n)
TxTSClk
TxTSClk
ECTION
TxSer
Connect the Transmit Payload Data Input Interface block to the Local Terminal Equipment
for Loop-timing applications
AVEFORMS OF THE SIGNALS CONNECTING THE
T
ERMINAL
F
Timeslot #0
c1 c2 c3 c4 c5
E
1
QUIPMENT WITH THE
2
Timeslot 0
Input Data
3
4
A B
5
6
C
7
D
8
OSCCLK D
c1 c2 c3 c4 c5
Timeslot #5
Input Data
Timeslot 5
188
A B
RIVEN
T
RANSMIT
C
D
D
c1 c2 c3 c4 c5
1
IVIDED CLOCK AS THE TIMING SOURCE OF THE
Timeslot #6
2
P
Timeslot 6
Input Data
3
AYLOAD
4
A B
5
6
C
7
D
D
8
ATA
I
NPUT
c1 c2 c3 c4 c5
Timeslot #23
I
NTERFACE BLOCK
Timeslot 23
Input Data
A B
REV. 1.0.1
C
D
F