XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 213

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
Payload and signaling data of Channel 0-3 are multiplexed onto the Transmit Serial Data pin of Channel 0.
Payload and signaling data of Channel 4-7 are multiplexed onto the Transmit Serial Data pin of Channel 4. The
Transmit Single-frame Synchronization signal of Channel 0 pulses HIGH at the beginning of the frame with data
from Channel 0-3 multiplexed together. The Transmit Single-frame Synchronization signal of Channel 4 pulses
HIGH at the beginning of the frame with data from Channel 4-7 multiplexed together. It is responsibility of the
Terminal Equipment to align the multiplexed transmit serial data with the Transmit Single-frame Synchronization
pulse. Additionally, each channel requires the local Terminal Equipment to provide a free-running 1.544 MHz
clock into the Transmit Serial Clock input.
The table below summaries the clock frequencies of TxSerClk_n and TxInClk_n inputs when the framer is
operating in multiplexed High-speed Back-plane mode.
The Transmit Serial Clock is always running at 1.544MHz for all the High-speed Back-plane Interface modes. It is
automatically the timing source of the Transmit Section of the framer in High-speed Back-plane Interface mode.
The Transmit Single-frame Synchronization signal should pulse HIGH or LOW for one bit period at the Framing
bit position of each DS1 frame. Length of the bit period depends on data rate of the High-speed Back-plane
Interface. The Transmit Synchronization Pulse Low bit of the Transmit Interface Control Register (TICR)
determines whether the Transmit Single-frame Synchronization signal is HIGH active or LOW active.
The table below shows configurations of the Transmit Synchronization Pulse LOW bit of the Transmit Interface
Control Register (TICR).
TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0xn0H, 0x20H)
Throughout the discussion of this datasheet, we assume that the Transmit Single-frame Synchronization signal
pulses HIGH unless stated otherwise.
The TxMSync_n signal, which is a multiplexed I/O pin, no longer functions as the Transmit Multi-frame
Synchronization Signal. Indeed, it becomes the Transmit Input Clock signal (TxInClk) of the High-speed Back-
plane Interface of the framer. The local Terminal Equipment should provide a free-running clock with the same
frequency as the High-speed Back-plane Interface to this input pin.
The following sections discuss details of how to operate the framer in different Back-plane interface speed mode
and how to connect the Transmit Payload Data Input Interface block to the local Terminal Equipment.
TRANSMIT MULTIPLEX ENABLE BIT = 1
T
N
M
RANSMIT
UMBER
ODE
B
3
IT
S
ELECT
0
0
1
1
I
NTERFACE
Synchronization
Pulse LOW
B
B
Transmit
IT
IT
1
N
AME
T
M
RANSMIT
ODE
S
B
ELECT
0
1
0
1
IT
I
R/W
NTERFACE
T
YPE
B
IT
0
0 - The Transmit Single-frame Synchronization signal will pulse HIGH indicat-
ing the beginning of a DS1 frame when the High-speed Back-plane Interface
is running at a mode other than the 1.544Mbit/s.
1 - The Transmit Single-frame Synchronization signal will pulse LOW indicat-
ing the beginning of a DS1 frame when the High-speed Back-plane Interface
is running at a mode other than the 1.544Mbit/s.
B
Bit-multiplexed 16.384Mbit/s
ACK
Multiplexed 12.352Mbit/s
HMVIP 16.384Mbit/s
H.100 16.384Mbit/s
-
PLANE
193
R
I
NTERFACE
ATE
D
ATA
B
IT
D
ESCRIPTION
1.544 MHz
1.544 MHz
1.544 MHz
1.544 MHz
T
X
S
ER
C
OCTAL T1/E1/J1 FRAMER
LK
T
X
MS
12.352 MHz
16.384 MHz
16.384 MHz
16.384 MHz
XRT84L38
YNC
/T
X
I
N
C
LK