XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 289

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
•
•
The Transmit Back-plane Interface is accepting data through TxSer_0 or TxSer_4 pins at 16.384Mbit/s. The
local Terminal Equipment multiplexes payload and signaling data of every four channels into one data stream.
Payload and signaling data of Channel 0-3 are multiplexed onto the Transmit Serial Data pin of Channel 0.
Payload and signaling data of Channel 4-7 are multiplexed onto the Transmit Serial Data pin of Channel 4.
Free-running clocks of 16.384MHz is supplied to the Transmit Input Clock pin of Channel 0 and Channel 4 of
the framer. The local Terminal Equipment provides multiplexed payload data at rising edge of this Transmit
Input Clock. The Transmit High-speed Back-plane Interface of the framer then latches incoming serial data at
falling edge of the clock.
The local Terminal Equipment maps four 2.048Mbit/s E1 data streams into this 16.384Mbit/s data stream as
described below:
FIRST OCTET OF 16.384MBIT/S DATA STREAM
THIRD OCTET OF 16.384MBIT/S DATA STREAM
FIFTH OCTET OF 16.384MBIT/S DATA STREAM
SEVENTH OCTET OF 16.384MBIT/S DATA STREAM
X
1. Payload data of four channels are repeated and grouped together in a byte-interleaved way. The first pay-
Y
Transmit Time-slot Indication clock (TxTSClk_n)
Transmit Time Slot indicator bits (TxTSb[4:0]_n)
: The Xth payload bit of Channel Y
load bit of Timeslot 0 of Channel 0 is sent first, followed by the second payload bit of Timeslot 0 of Channel
0 and so on. After all the bits of Timeslot 0 of Channel 0 is sent repeatedly, the Terminal Equipment will
start sending the payload bits of Timeslot 0 of Channel 1 and 2. The payload bits of Timeslot 0 of Channel
3 are sent the last.
After the payload bits of Timeslot 0 of all four channels are sent, it comes the payload bits of Timeslot 1 of
Channel 0 and so on. The table below demonstrates how payload bits of four channels are mapped into
the 16.384Mbit/s data stream.
B
B
B
B
1
1
1
1
IT
IT
IT
IT
0
1
2
3
0
0
0
0
B
B
B
B
1
1
1
1
IT
IT
IT
IT
0
1
2
3
1
1
1
1
B
B
B
B
2
2
2
2
IT
IT
IT
IT
0
1
2
3
2
2
2
2
B
B
B
B
2
2
2
2
IT
IT
IT
IT
0
1
2
3
3
3
3
3
269
B
B
B
B
3
3
3
3
IT
IT
IT
IT
0
1
2
3
4
4
4
4
B
B
B
B
3
3
3
3
IT
IT
IT
IT
0
1
2
3
5
5
5
5
OCTAL T1/E1/J1 FRAMER
B
B
B
B
4
4
4
4
IT
IT
IT
IT
0
1
2
3
6
6
6
6
XRT84L38
B
B
B
B
4
4
4
4
IT
IT
IT
IT
0
1
2
3
7
7
7
7