XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 429
XRT84L38IB
Manufacturer Part Number
XRT84L38IB
Description
Network Controller & Processor ICs 8 Ch T1/E1 Framer
Manufacturer
Exar Corporation
Datasheet
1.XRT84L38.pdf
(453 pages)
Specifications of XRT84L38IB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REV. 1.0.1
13.2
13.2.1
XRT84L38 allows user to extract data link information from incoming DS1 frames. The data link information in
DS1raming format mode can be extracted to the following:
•
•
•
The Receive Data Link Source Select [1:0] bits, within the Receive Data Link Select Register (RSDLSR)
determine destinations of the data link bits (Facility Data Link (FDL) bits in ESF framing format mode, Signaling
Framing (Fs) bits in SLC®96 framing format mode and Remote Signaling (R) bits in T1DM framing format
mode) extracted from the incoming DS1 frames.
The table below shows configuration of the Receive Data Link Source Select [1:0] bits of the Receive Data Link
Select Register (RSDLSR).
RECEIVE DATA LINK SELECT REGISTER (RSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0CH)
If the Receive Data Link Source Select bits of the Receive Data Link Select Register are set to 00, the Receive
HDLC Controller block becomes output destination of the data link bits in incoming DS1 frames.
Each of the eight framers within the XRT84L38 device contains a DS1 Receive High-level Data Link Controller
(HDLC) block. The function of this block is to establish a serial data link channel in DS1 mode through the
following:
•
•
•
•
Data link bits are automatically inserted into the Facility Data Link (FDL) bits in ESF framing format mode,
Signaling Framing (Fs) bits in SLC®96 framing format mode and Remote Signaling (R) bits in T1DM framing
format mode or forced to 1 by the framer. Additionally, XRT84L38 allows the user to define any one of ones of
the twenty-four DS0 timeslots to be D or E channel. We will discuss how to configure XRT84L38 to Receive
data link information through D or E channels in later section.
The DS1 Receive HDLC Controller block contains three major functional modules associated with DS1 framing
formats. They are the:
•
•
•
N
DS1 Receive Overhead Output Interface Block
DS1 Receive HDLC Controller
DS1 Receive Serial Output Interface
Facility Data Link (FDL) bits in ESF framing format mode
Signaling Framing (Fs) bits in SLC®96 framing format mode
Remote Signaling (R) bits in T1DM framing format mode
D or E signaling timeslot channel
SLC®96 Data Link Controller
LAPD Controller
Bit-Oriented Signaling Processor.
UMBER
B
1-0
IT
DS1 Receive HDLC Controller Block
Description of the DS1 Receive HDLC Controller Block
Source Select [1:0]
Receive Data Link
B
IT
N
AME
B
IT
R/W
T
YPE
00 - The data link bits extracted from the incoming DS1 frame are sent to
the Receive HDLC Controller.
01 - The data link bits extracted from the incoming DS1 frame are sent to
the Receive Serial Data Output Interface via the RxSer_n pins.
10 - The data link bits extracted from the incoming DS1 frame are sent to
the Receive Overhead Output Interface via the RxOH_n pins.
11 - The data link bits are forced into 1.
409
B
IT
D
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38
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