XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 311

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
The timing diagram of input signals to the framer when running at 4.096Mbit/s mode is shown in
(This interface mode is the same as running at 2.048 MHz. The only difference is that the Receive Serial Clock
runs four times faster at 8.192MHz)
When the Receive Multiplex Enable bit is set to zero and the Receive Interface Mode Select [1:0] bits are set to
11, the Receive Back-plane interface of framer is running at a clock rate of 8.192MHz.
The interface consists of the following pins:
•
•
•
•
•
•
The Receive Back-plane interface is pumping out data through RxSer_n at an E1 equivalent data rate of
2.048Mbit/s. The local Terminal Equipment supplies a free-running 8.192MHz clock to the Receive Serial
Clock input. The Receive High-speed Back-plane Interface of the framer then sends out serial data at every
other four rising edge of the Receive Serial Clock. The local Terminal Equipment samples the serial data at
every other four falling edge of the clock.
The Receive Single-frame Synchronization input signal (RxSync_n) should pulse HIGH at the beginning of the
256-bit frame indicating start of the frame. By sampling the HIGH pulse of the Receive Single-frame
Synchronization signal, the framer can identity the beginning of an E1 frame and start pumping payload data
out.
F
6.2.3.3
IGURE
Data input (RxSer_n)
Receive Serial Clock Input signal (RxSerClk_n)
Receive Single-frame Synchronization Input signal (RxSync_n)
Receive Input Clock (RxInClk_n)
Receive Time-slot Indication clock (RxTSClk_n)
Receive Time Slot indicator bits (RxTSb[4:0]_n)
TxSerClk (4MHz)
TxSerClk (2MHz)
TxSerClk (INV)
TxSer
TxSync(input)
TxChn[0]/TxSig
TxChClk(INV)
TxChn[1]/TxFrTD
Note: The following signals are not aligned with the signals shown above. The TxChClk is derived from 1.544MHz transmit clock.
90. T
IMING
E1 Receive Input Interface - 8.192 MHz
F
D
IAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT
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1
2
3
4
A B
5
6
7
C
D
8
1
1
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2
2
3
3
291
4
4
5
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5
6
6
7
7
C
8
D
8
1
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2
3
4
5
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6
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7
D
8
4.096M
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OCTAL T1/E1/J1 FRAMER
BIT
/
S MODE
1
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1
XRT84L38
2
2
Figure 90
3
3
4
4
A B
5
5
6
6
C
7
7
D
8
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8