XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 280

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
Transmit Single-frame Synchronization signal of Channel 0 pulses HIGH at the beginning of the frame with
data from Channel 0-3 multiplexed together. The Transmit Single-frame Synchronization signal of Channel 4
pulses HIGH at the beginning of the frame with data from Channel 4-7 multiplexed together. It is responsibility
of the Terminal Equipment to align the multiplexed transmit serial data with the Transmit Single-frame
Synchronization pulse. Additionally, each channel requires the local Terminal Equipment to provide a free-
running 2.048 MHz clock into the Transmit Serial Clock input.
The table below summaries the clock frequencies of TxSerClk_n and TxInClk_n inputs when the framer is
operating in multiplexed High-speed Back-plane mode.
TRANSMIT MULTIPLEX ENABLE BIT = 1
The Transmit Serial Clock is always running at 1.544MHz for all the High-speed Back-plane Interface modes. It
is automatically the timing source of the Transmit Section of the framer in High-speed Back-plane Interface
mode.
The Transmit Single-frame Synchronization signal should pulse HIGH or LOW for one bit period at the First bit
position of each E1 frame. Length of the bit period depends on data rate of the High-speed Back-plane
Interface. The Transmit Synchronization Pulse Low bit of the Transmit Interface Control Register (TICR)
determines whether the Transmit Single-frame Synchronization signal is HIGH active or LOW active.
The table below shows configurations of the Transmit Synchronization Pulse LOW bit of the Transmit Interface
Control Register (TICR).
TRANSMIT INTERFACE CONTROL REGISTER (TICR) (NDIRECT ADDRESS = 0XN0H, 0X20H)
Throughout the discussion of this datasheet, we assume that the Transmit Single-frame Synchronization signal
pulses HIGH unless stated otherwise.
The TxMSync_n signal, which is a multiplexed I/O pin, no longer functions as the Transmit Multi-frame
Synchronization Signal. Indeed, it becomes the Transmit Input Clock signal (TxInClk) of the High-speed Back-
plane Interface of the framer. The local Terminal Equipment should provide a free-running clock with the same
frequency as the High-speed Back-plane Interface to this input pin.
The following sections discuss details of how to operate the framer in different Back-plane interface speed
mode and how to connect the Transmit Payload Data Input Interface block to the local Terminal Equipment.
When the Transmit Multiplex Enable bit is set to zero and the Transmit Interface Mode Select [1:0] bits are set
to 01, the Transmit Back-plane interface of framer is running at a data rate of 2.048Mbit/s.
6.1.3.1
N
T
M
RANSMIT
UMBER
B
ODE
3
IT
S
ELECT
0
0
1
1
I
NTERFACE
Synchronization
E1 Transmit Input Interface - MVIP 2.048 MHz
Pulse LOW
B
B
Transmit
IT
IT
N
1
AME
T
M
RANSMIT
ODE
B
S
ELECT
IT
R/W
0
1
0
1
I
T
NTERFACE
YPE
B
IT
0 - The Transmit Single-frame Synchronization signal will pulse HIGH indicat-
ing the beginning of an E1 frame when the High-speed Back-plane Interface is
running at a mode other than the XRT84V24 Compatible 2.048Mbit/s.
1 - The Transmit Single-frame Synchronization signal will pulse LOW indicat-
ing the beginning of an E1 frame when the High-speed Back-plane Interface is
running at a mode other than the XRT84V24 Compatible 2.048Mbit/s.
0
I
NTERFACE
HMVIP 16.384Mbit/s
H.100 16.384Mbit/s
Bit-multiplexed
16.384Mbit/s
B
ACK
260
-
-
PLANE
D
ATA
R
ATE
B
IT
D
ESCRIPTION
2.048 MHz
2.048 MHz
2.048 MHz
T
X
S
ER
-
C
LK
T
X
16.384 MHz
16.384 MHz
16.384 MHz
MS
YNC
-
/T
REV. 1.0.1
X
C
LK