PIC24FJ16MC102-I/SP Microchip Technology, PIC24FJ16MC102-I/SP Datasheet - Page 111

• Manufacturer Part Number: PIC24FJ16MC102-I/SP
• Description: 16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16MC102-I/SP

• Featured Product: PIC24FJ/33FJ MCUs & dsPIC® DSCs
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 10-2:
10.4.3
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping are
needed to prevent accidental configuration changes.
PIC24FJ16MC101/102 devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
10.4.3.1
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by the IOLOCK bit
(OSCCON<6>). Setting IOLOCK prevents writes to the
control registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1.
2.
3.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
© 2011 Microchip Technology Inc.
Note:
Write 0x46 to OSCCON<7:0>.
Write 0x57 to OSCCON<7:0>.
Clear (or set) IOLOCK as a single operation.
Function
C1OUT
C2OUT
C3OUT
U1RTS
CTPLS
NULL
U1TX
OC1
OC2
SS1
CONTROLLING CONFIGURATION
CHANGES
MPLAB
language functions for unlocking the
OSCCON register:
See MPLAB IDE Help for more
information.
Control Register Lock Sequence
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
®
C30
provides
RPnR<4:0>
00000
00001
00010
00011
00100
01001
10010
10011
11101
11110
built-in
Preliminary
C
RPn tied to default port pin
RPn tied to Comparator 1 Output
RPn tied to Comparator 2 Output
RPn tied to UART1 Transmit
RPn tied to UART1 Ready To Send
RPn tied to SPI1 Slave Select Output
RPn tied to Output Compare 1
RPn tied to Output Compare 2
RPn tied to CTMU Pulse Output
RPn tied to Comparator 3 Output
10.4.3.2
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a configuration mismatch Reset will
be triggered.
10.4.3.3
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY
(FOSC<IOL1WAY>) configuration bit blocks the
IOLOCK bit from being cleared after it has been set
once. If IOLOCK remains set, the register unlock
procedure will not execute, and the peripheral pin
select control registers cannot be written to. The only
way to clear the bit and re-enable peripheral remapping
is to perform a device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
peripheral pin select registers.
10.5
The
implement 21 registers for remappable peripheral
configuration:
• Input Remappable Peripheral Registers (13)
• Output Remappable Peripheral Registers (8)
Note:
PIC24FJ16MC101/102
PIC24FJ16MC101/102
Peripheral Pin Select Registers
Input and Output Register values can only
be changed if OSCCON<IOLOCK> = 0.
See
Lock Sequence”
sequence.
Configuration Bit Pin Select Lock
Continuous State Monitoring
Output Name
Section 10.4.3.1 “Control Register
for a specific command
family
DS39997B-page 111
of
devices