PIC24FJ16MC102-I/SP Microchip Technology, PIC24FJ16MC102-I/SP Datasheet - Page 148

• Manufacturer Part Number: PIC24FJ16MC102-I/SP
• Description: 16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16MC102-I/SP

• Featured Product: PIC24FJ/33FJ MCUs & dsPIC® DSCs
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ16MC101/102
REGISTER 15-9:
DS39997B-page 148
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13-8
bit 7
bit 6-3
bit 2
bit 1
bit 0
Note 1:
FLTAM
R/W-0
U-0
—
2:
3:
4:
5:
On PIC24FJ16MC101 (20-pin) devices, the FLTA1 pin is supported, but requires an external pull-down
resistor for correct functionality.
On PIC24FJ16MC102 (28-pin) devices, the FLTA1 and FLTB1 pins are supported and do not require an
external pull-down resistor.
The PxFLTACON register is a write-protected register. Refer to
Registers”
Comparator outputs are not internally connected to the PWM Fault control logic. If using the Comparator
modules for Fault generation, the user must externally connect the desired comparator output pin to the
dedicated FLTA1 or FLTB1 input pin.
During any reset event, the FLTA1 pin is enabled by default and must be cleared as described in
Section 15.2 “PWM
Unimplemented: Read as ‘0’
FAOVxH<3:1>:FAOVxL<3:1>: Fault Input A PWM Override Value bits
1 = The PWM output pin is driven active on an external Fault input event
0 = The PWM output pin is driven inactive on an external Fault input event
FLTAM: Fault A Mode bit
1 = The Fault A input pin functions in the Cycle-by-Cycle mode
0 = The Fault A input pin latches all control pins to the programmed states in PxFLTACON<13:8>
Unimplemented: Read as ‘0’
FAEN3: Fault Input A Enable bit
1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input A
0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input A
FAEN2: Fault Input A Enable bit
1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input A
0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A
FAEN1: Fault Input A Enable bit
1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input A
0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A
U-0
U-0
—
—
PxFLTACON: FAULT A CONTROL REGISTER
for more information on the unlock sequence.
W = Writable bit
‘1’ = Bit is set
Faults”.
FAOV3H
R/W-0
U-0
—
FAOV3L
R/W-0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
FAOV2H
R/W-0
U-0
—
Section 15.3 “Write-protected
(1,2,3,4,5)
FAOV2L
FAEN3
R/W-0
R/W-1
© 2011 Microchip Technology Inc.
x = Bit is unknown
FAOV1H
FAEN2
R/W-0
R/W-1
FAOV1L
FAEN1
R/W-0
R/W-1
bit 8
bit 0