PIC24FJ16MC102-I/SP Microchip Technology, PIC24FJ16MC102-I/SP Datasheet - Page 27

• Manufacturer Part Number: PIC24FJ16MC102-I/SP
• Description: 16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16MC102-I/SP

• Featured Product: PIC24FJ/33FJ MCUs & dsPIC® DSCs
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.0
FIGURE 4-1:
© 2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: It
MEMORY ORGANIZATION
of the PIC24FJ16MC101/102 family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 3. “Data Memory”
(DS39717) and Section 4. “Program
Memory” (DS39715) in the “PIC24F
Family Reference Manual”, which are
available from the Microchip web site
(www.microchip.com).
specifications in
cal Characteristics”
supercede any specifications that may be
provided in PIC24F Family Reference
Manual sections.
Note 1:
is
important
PROGRAM MEMORY MAP FOR PIC24FJ16MC101/102 DEVICES
On reset, these bits are automatically copied into the device Configuration shadow registers.
Section 26.0 “Electri-
to
of this data sheet,
note
that
Alternate Vector Table
Interrupt Vector Table
Device Configuration
Flash Configuration
Shadow Registers
(5.6K instructions)
the
Preliminary
GOTO Instruction
Unimplemented
Reset Address
Flash Memory
User Program
(Read ‘0’s)
DEVID (2)
Reserved
Reserved
Words
Reserved
(1)
The
separate program and data memory spaces and
buses. This architecture also allows the direct access
of program memory from the data space during code
execution.
4.1
The
PIC24FJ16MC101/102 devices is 4M instructions. The
space is addressable by a 24-bit value derived either
from the 23-bit Program Counter (PC) during program
execution, or from table operation or data space
remapping as described in
Program and Data Memory
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The memory map for the PIC24FJ16MC101/102 family
of devices is shown in
PIC24FJ16MC101/102
program
PIC24FJ16MC101/102
Program Address Space
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x002BFA
0x002BFC
0x002BFE
0x002COO
0x7FFFFE
0x800000
0xF7FFFE
0xF80000
0xF80017
0xF80018
0xFEFFFE
0xFF0000
0xFFFFFE
address
Figure
memory
Section 4.4 “Interfacing
Spaces”.
4-1.
architecture
DS39997B-page 27
space
features
of
the