PIC24FJ16MC102-I/SP Microchip Technology, PIC24FJ16MC102-I/SP Datasheet - Page 21

• Manufacturer Part Number: PIC24FJ16MC102-I/SP
• Description: 16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16MC102-I/SP

• Featured Product: PIC24FJ/33FJ MCUs & dsPIC® DSCs
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.0
The PIC24FJ16MC101/102 CPU module has a 16-bit
(data) modified Harvard architecture with an enhanced
instruction set and addressing modes. The CPU has a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M by 24 bits of user program memory
space. The actual amount of program memory
implemented
instruction prefetch mechanism is used to help
maintain
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program
instruction and the table instructions. Overhead-free,
single-cycle program loop constructs are supported
using the REPEAT instruction, which is interruptible at
any point.
The PIC24FJ16MC101/102 devices have sixteen, 16-bit
working registers in the programmer’s model. Each of the
working registers can serve as a data, address or
address offset register. The 16th working register (W15)
operates as a software Stack Pointer (SP) for interrupts
and calls.
© 2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: It
3: Some registers and associated bits
CPU
flow,
throughput
of the PIC24FJ16MC101/102 family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS39703) in the “PIC24F Family Refer-
ence Manual”, which is available from the
Microchip web site (www.microchip.com).
specifications in
cal Characteristics”
supercede any specifications that may be
provided in PIC24F Family Reference
Manual sections.
described in this section may not be avail-
able on all devices. Refer to
“Memory Organization”
sheet for device-specific register and bit
information.
varies
is
the
important
double-word
by
and
device.
Section 26.0 “Electri-
provides
to
of this data sheet,
note
move
A
in this data
Section 4.0
single-cycle
predictable
that
(MOV.D)
the
Preliminary
The PIC24FJ16MC101/102 instruction set includes
many addressing modes and is designed for optimum
C
PIC24FJ16MC101/102
executing a data (or program data) memory read, a
working register (data) read, a data memory write, and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in
and
PIC24FJ16MC101/102 is shown in
3.1
The data space can be linearly addressed as 32K words
or 64 Kbytes using an Address Generation Unit (AGU).
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K
program word boundary defined by the 8-bit Program
Space Visibility Page register (PSVPAG). The program to
data space mapping feature lets any instruction access
program space as if it were data space.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers, but may
be used as general purpose RAM.
3.2
The PIC24FJ16MC101/102 features a 17-bit by 17-bit,
single-cycle multiplier. The multiplier can perform
signed, unsigned and mixed-sign multiplication. Using
a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication
possible.
The PIC24FJ16MC101/102 supports 16/16 and 32/16
integer divide operations. All divide instructions are
iterative operations. They must be executed within a
REPEAT loop, resulting in a total execution time of 19
instruction cycles. The divide operation can be
interrupted during any of those 19 cycles without loss
of data.
A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.
compiler
PIC24FJ16MC101/102
the
Data Addressing Overview
Special MCU Features
programmer’s
efficiency.
makes
devices
mixed-sign
For
model
most
Figure
are
DS39997B-page 21
multiplication
capable
instructions,
3-2.
Figure
for
3-1,
the
of