PIC24FJ16MC102-I/SP Microchip Technology, PIC24FJ16MC102-I/SP Datasheet - Page 46

• Manufacturer Part Number: PIC24FJ16MC102-I/SP
• Description: 16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16MC102-I/SP

• Featured Product: PIC24FJ/33FJ MCUs & dsPIC® DSCs
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ16MC101/102
4.4.1
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within the
program space. This is concatenated with a 16-bit EA to
arrive at a full 24-bit program space address. In this for-
mat, the MSb of TBLPAG is used to determine if the
operation occurs in the user memory (TBLPAG<7> = 0)
or the configuration memory (TBLPAG<7> = 1).
TABLE 4-28:
DS39997B-page 46
Instruction Access
(Code Execution)
TBLRD/TBLWT
(Byte/Word Read/Write)
Program Space Visibility
(Block Remap/Read)
Note 1:
Access Type
Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
ADDRESSING PROGRAM SPACE
PROGRAM SPACE ADDRESS CONSTRUCTION
User
User
Configuration
User
Access
Space
Preliminary
<23>
0
0
0
TBLPAG<7:0>
TBLPAG<7:0>
0xxx xxxx
1xxx xxxx
0xx
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the MSb
of the EA is ‘1’, PSVPAG is concatenated with the lower
15 bits of the EA to form a 23-bit program space
address. Unlike table operations, this limits remapping
operations strictly to the user memory area.
Table 4-28
created for table operations and remapping accesses
from the data EA.
<22:16>
xxxx xxxx
PSVPAG<7:0>
xxxx
Program Space Address
and
xxxx
PC<22:1>
Figure 4-5
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
<15>
xxxx
© 2011 Microchip Technology Inc.
show how the program EA is
xxx xxxx xxxx xxxx
Data EA<15:0>
Data EA<15:0>
xxxx xxx0
<14:1>
Data EA<14:0>
(1)
<0>
0