PIC24FJ16MC102-I/SP Microchip Technology, PIC24FJ16MC102-I/SP Datasheet - Page 59

• Manufacturer Part Number: PIC24FJ16MC102-I/SP
• Description: 16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16MC102-I/SP

• Featured Product: PIC24FJ/33FJ MCUs & dsPIC® DSCs
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.2
A POR circuit ensures the device is reset from power-
on. The POR circuit is active until V
V
delay T
become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate require-
ments to generate the POR. Refer to
“Electrical Characteristics”
The POR status bit (POR) in the Reset Control register
(RCON<0>) is set to indicate the Power-on Reset.
FIGURE 6-3:
© 2011 Microchip Technology Inc.
POR
SYSRST
SYSRST
SYSRST
threshold and the delay T
POR
POR
V
V
V
DD
DD
DD
ensures the internal device bias circuits
V
DD
dips before PWRT expires
BROWN-OUT SITUATIONS
for details.
POR
has elapsed. The
DD
Section 26.0
crosses the
Preliminary
T
BOR
+ T
T
T
PWRT
BOR
BOR
6.3
The on-chip regulator has a BOR circuit that resets the
device when the V
device operation. The BOR circuit keeps the device in
Reset until V
delay T
voltage regulator output becomes stable.
The BOR status bit (BOR) in the Reset Control register
(RCON<1>) is set to indicate the Brown-out Reset.
The device will not run at full speed after a BOR as the
V
operation. The PWRT provides power-up time delay
(T
stabilized at the appropriate levels for full-speed oper-
ation before the SYSRST is released.
Refer to
details.
Figure 6-3
Reset delay (T
rises above the V
DD
+ T
PWRT
+ T
PWRT
should rise to acceptable levels for full-speed
PWRT
) to ensure that the system power supplies have
BOR
PIC24FJ16MC101/102
BOR and PWRT
Section 23.0 “Special Features”
shows the typical brown-out scenarios. The
has elapsed. The delay T
DD
BOR
crosses the V
BOR
DD
+ T
is too low (V
trip point.
PWRT
) is initiated each time V
V
V
V
BOR
BOR
BOR
BOR
DD
< V
threshold and the
DS39997B-page 59
BOR
BOR
ensures the
) for proper
for further
DD