PIC24FJ16MC102-I/SP Microchip Technology, PIC24FJ16MC102-I/SP Datasheet - Page 61

• Manufacturer Part Number: PIC24FJ16MC102-I/SP
• Description: 16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16MC102-I/SP

• Featured Product: PIC24FJ/33FJ MCUs & dsPIC® DSCs
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.9
An illegal condition device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset
Flag bit (IOPUWR) in the Reset Control register
(RCON<14>) is set to indicate the illegal condition
device Reset.
6.9.1
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The illegal opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 0x3F,
which is an illegal opcode value.
6.9.2
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
TABLE 6-3:
© 2011 Microchip Technology Inc.
Note: All Reset flag bits can be set or cleared by user software.
TRAPR (RCON<15>)
IOPWR (RCON<14>)
SLEEP (RCON<3>)
Illegal Condition Device Reset
WDTO (RCON<4>)
EXTR (RCON<7>)
SWR (RCON<6>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
CM (RCON<9>)
ILLEGAL OPCODE RESET
UNINITIALIZED W REGISTER
RESET
Flag Bit
RESET FLAG BIT OPERATION
W register access or Security Reset
Illegal opcode or uninitialized
PWRSAV #SLEEP instruction
PWRSAV #IDLE instruction
Configuration Mismatch
Preliminary
Trap conflict event
RESET instruction
WDT Time-out
MCLR Reset
POR, BOR
Set by:
POR
6.9.3
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a pro-
tected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
6.10
The user application can read the Reset Control regis-
ter (RCON) after any device Reset to determine the
cause of the Reset.
Table 6-3
operation.
Note:
PIC24FJ16MC101/102
Using the RCON Status Bits
provides a summary of Reset flag bit
SECURITY RESET
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
CLRWDT instruction, POR, BOR
PWRSAV instruction,
Cleared by:
POR, BOR
POR, BOR
POR, BOR
POR, BOR
POR, BOR
POR, BOR
POR
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DS39997B-page 61