PIC24FJ16MC102-I/SP Microchip Technology, PIC24FJ16MC102-I/SP Datasheet - Page 215

• Manufacturer Part Number: PIC24FJ16MC102-I/SP
• Description: 16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16MC102-I/SP

• Featured Product: PIC24FJ/33FJ MCUs & dsPIC® DSCs
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

23.0
PIC24FJ16MC101/102
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible configuration
• Watchdog Timer (WDT)
• Code Protection
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit emulation
© 2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: It
3: Some registers and associated bits
SPECIAL FEATURES
of the PIC24FJ16MC101/102 devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 9. “Watchdog Timer (WDT)”
(DS39697) and Section 33. “Program-
ming and Diagnostics” (DS39716) in
the “PIC24F Family Reference Manual”,
which are available from the Microchip
web site (www.microchip.com).
specifications in
cal Characteristics”
supercede any specifications that may be
provided in PIC24F Family Reference
Manual sections.
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
is
important
devices
Section 26.0 “Electri-
to
of this data sheet,
include
note
that
several
the
Preliminary
in
23.1
The Configuration Shadow register bits can be config-
ured (read as ‘0’), or left unprogrammed (read as ‘1’),
to select various device configurations. These read-
only bits are mapped starting at program memory loca-
tion 0xF80000. A detailed explanation of the various bit
functions is provided in
Note that address 0xF80000 is beyond the user pro-
gram memory space and belongs to the configuration
memory space (0x800000-0xFFFFFF) which can only
be accessed using table reads.
In PIC24FJ16MC101/102 devices, the configuration
bytes are implemented as volatile memory. This means
that configuration data must be programmed each time
the device is powered up. Configuration data is stored in
the two words at the top of the on-chip program memory
space, known as the Flash Configuration Words. Their
specific locations are shown in
packed representations of the actual device Configura-
tion bits, whose actual locations are distributed among
several locations in configuration space. The configura-
tion data is automatically loaded from the Flash Config-
uration Words to the proper Configuration registers
during device Resets.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The upper byte of all Flash Configuration Words in pro-
gram memory should always be ‘1111 1111’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
Note:
Note:
PIC24FJ16MC101/102
Configuration Bits
Configuration data is reloaded on all types
of device Resets.
Performing a page erase operation on the
last page of program memory clears the
Flash Configuration Words, enabling code
protection as a result. Therefore, users
should avoid performing page erase
operations on the last page of program
memory.
Table
23-3.
Table
DS39997B-page 215
23-2. These are