FW82801EB Intel, FW82801EB Datasheet - Page 123

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.8
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Intel
®
Table 45. Interrupt Controller Core Connections
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: Active-low interrupt sources (e.g., the PIRQ#s) are inverted inside the ICH5. In the following
8259 Interrupt Controllers (PIC) (D31:F0)
The ICH5 incorporates the functionality of two 8259 interrupt controllers that provide system
interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard
controller, serial ports, parallel ports, floppy disk, IDE, mouse, and DMA channels. In addition,
this interrupt controller can support the PCI based interrupts, by mapping the PCI interrupt onto the
compatible ISA interrupt line. Each 8259 core supports eight interrupts, numbered 0
shows how the cores are connected.
The ICH5 cascades the slave controller onto the master controller through master controller
interrupt input 2. This means there are only 15 possible interrupts for the ICH5 PIC.
Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2, IRQ8#, and
IRQ13.
Note that previous PIIXn devices internally latched IRQ12 and IRQ1 and required a port 60h read
to clear the latch. The ICH5 can be programmed to latch IRQ12 or IRQ1 (see bit 11 and bit 12 in
General Control Register, D31:F0, offset D0h).
descriptions of the 8259s, the interrupt levels are in reference to the signals at the internal interface
of the 8259s, after the required inversions have occurred. Therefore, the term “high” indicates
“active,” which means “low” on an originating PIRQ#.
Master
Slave
8259
Input
8259
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Internal
Keyboard
Internal
Serial Port A
Serial Port B
Parallel Port / Generic
Floppy Disk
Parallel Port / Generic
Internal Real Time Clock
Generic
Generic
Generic
PS/2 Mouse
Internal
Primary IDE cable
Secondary IDE Cable
Typical Interrupt
Source
Internal Timer / Counter 0 output / HPET#0
IRQ1 via SERIRQ
Slave controller INTR output
IRQ3 via SERIRQ
IRQ4 via SERIRQ
IRQ5 via SERIRQ
IRQ6 via SERIRQ
IRQ7 via SERIRQ
Internal RTC / HPET #1
IRQ9 via SERIRQ
IRQ10 via SERIRQ
IRQ11 via SERIRQ
IRQ12 via SERIRQ
State Machine output based on processor FERR#
assertion.
IRQ14 from input signal (primary IDE in legacy mode only)
or via SERIRQ
IRQ15 from input signal (secondary IDE in legacy mode
only) or via SERIRQ
Connected Pin / Function
Functional Description
–
7.
Table 45
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