FW82801EB Intel, FW82801EB Datasheet - Page 523

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

14.2.2
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: A read to this register will clear the byte pointer of the 32-byte buffer.
HST_CNT—Host Control Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
Bit
Bit
2
1
0
7
6
5
DEV_ERR — R/WC.
0 = Software clears this bit by writing a 1 to it. The ICH5 will then deassert the interrupt or SMI#.
1 = The source of the interrupt or SMI# was due to one of the following:
INTR — R/WC (special). This bit can only be set by termination of a command. INTR is not
dependent on the INTREN bit of the Host Controller Register (offset 02h). It is only dependent on the
termination of the command. If the INTREN bit is not set, then the INTR bit will be set, although the
interrupt will not be generated. Software can poll the INTR bit in this non-interrupt case.
0 = Software clears this bit by writing a 1 to it. The ICH5 then deasserts the interrupt or SMI#.
1 = The source of the interrupt or SMI# was the successful completion of its last command.
HOST_BUSY — RO.
0 = Cleared by the ICH5 when the current transaction is completed.
1 = Indicates that the ICH5 is running a command from the host interface. No SMB registers should
PEC_EN . — R/W.
0 = SMBus host controller does not perform the transaction with the PEC phase appended.
1 = Causes the host controller to perform the SMBus transaction with the Packet Error Checking
START — WO.
0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status register
1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All registers
LAST_BYTE — WO. This bit is used for Block Read commands.
1 = Software sets this bit to indicate that the next byte will be the last byte to be received for the
NOTE: Once the SECOND_TO_STS bit in TCO2_STS register (D31:F0, TCOBASE+6h, bit 1) is
be accessed while this bit is set, except the BLOCK DATA BYTE Register. The BLOCK DATA
BYTE Register can be accessed when this bit is set only when the SMB_CMD bits in the Host
Control Register are programmed for Block command or I
in order to check the DONE_STS bit.
phase appended. For writes, the value of the PEC byte is transferred from the PEC Register.
For reads, the PEC byte is loaded in to the PEC Register. This bit must be written prior to the
write in which the START bit is set.
(offset 00h) can be used to identify when the Intel
should be setup prior to writing a 1 to this bit position.
block. This causes the ICH5 to send a NACK (instead of an ACK) after receiving the last byte.
•Illegal Command Field,
•Unclaimed Cycle (host initiated),
•Host Device Time-out Error.
set, the LAST_BYTE bit also gets set. While the SECOND_TO_STS bit is set, the
LAST_BYTE bit cannot be cleared. This prevents the ICH5 from running some of the
SMBus commands (Block Read/Write, I
02h
00h
Description
Description
Attribute:
Size:
2
C Read, Block I
SMBus Controller Registers (D31:F3)
®
ICH5 has finished the command.
2
C Read command. This is necessary
2
C Write).
R/W, WO
8-bits
523