FW82801EB Intel, FW82801EB Datasheet - Page 237

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 111. Process Call Protocol with PEC
82801EB ICH5 / 82801ER ICH5R Datasheet
Block Read/Write
The ICH5 contains a 32-byte buffer for read and write data which can be enabled by setting bit 1 of
the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a single byte of buffering.
This 32-byte buffer is filled with write data before transmission, and filled with read data on
reception. In the ICH5, the interrupt is generated only after a transmission or reception of 32 bytes,
or when the entire byte count has been transmitted/received.
This requires the ICH5 to check the byte count field. Currently, the byte count field is transmitted
but ignored by the hardware as software will end the transfer after all bytes it cares about have been
sent or received.
For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and AAC bits to
0 when running this command.
SMBus mode: The block write begins with a slave address and a write condition. After the
command code the ICH5 issues a byte count describing how many more bytes will follow in the
message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by
20 bytes of data. The byte count may not be 0. A Block Read or Write is allowed to transfer a
maximum of 32 data bytes.
18:11
27:20
36:29
45:39
55:48
64:57
73:66
Bit
8:2
10
19
28
37
38
46
47
56
65
74
75
1
9
Start
Slave Address — 7 bits
Write
Acknowledge from Slave
Command code — 8 bits
Acknowledge from slave
Data byte Low — 8 bits
Acknowledge from slave
Data Byte High — 8 bits
Acknowledge from slave
Repeated Start
Slave Address — 7 bits
Read
Acknowledge from slave
Data Byte Low from slave — 8 bits
Acknowledge
Data Byte High from slave — 8 bits
Acknowledge
PEC from slave
NOT acknowledge
Stop
Description
Functional Description
237