FW82801EB Intel, FW82801EB Datasheet - Page 657

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 206. Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
Command Register Primary
Status Register Primary
Descriptor Table Pointer
Primary
Command Register
Secondary
Status Register Secondary
Descriptor Table Pointer
Secondary
USB Base Address is set at Section 12.1.10, “BASE—Base Address Register (USB—D29:F0/F1/F2/F3)”
USB Command Register
USB Status Register
USB Interrupt Enable
USB Frame Number
USB Frame List Base
Address
USB Start of Frame Modify
Port 0, 2, 4 Status/Control
Port 1, 3, 5 Status/Control
Loop Back Test Data
Host Status
Host Control
Host Command
Transmit Slave Address
Host Data 0
Host Data 1
Block Data Byte
BM_BASE is set at Section 10.1.12, “SCMD_BAR—Secondary Command Block Base Address Register (IDE
SMB_BASE is set at Section 14.1.8, “SMB_BASE—SMBUS Base Address Register (SMBUS—D31:F3)” on
®
Register Name
ICH5 Variable I/O Registers (Sheet 3 of 6)
SMBus I/O Registers at SMB_BASE + Offset
USB I/O Registers at Base Address + Offset
BMIDE I/O Registers at BM_BASE + Offset
0C – 0F
Offset
08 – 0B
04 – 07
00 – 01
02 – 03
04 – 05
06 – 07
10 – 11
12 – 13
18h
00h
02h
03h
04h
05h
06h
07h
0A
0C
00
02
08
D31:F1)” on page 421
Section 10.2.1, “BMIC[P,S]—Bus Master IDE Command
Register (IDE—D31:F1)” on page 431
Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status Register
(IDE—D31:F1)” on page 432
Section 10.2.3, “BMID[P,S]—Bus Master IDE Descriptor Table
Pointer Register (IDE—D31:F1)” on page 432
Section 10.2.1, “BMIC[P,S]—Bus Master IDE Command
Register (IDE—D31:F1)” on page 431
Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status Register
(IDE—D31:F1)” on page 432
Section 10.2.3, “BMID[P,S]—Bus Master IDE Descriptor Table
Pointer Register (IDE—D31:F1)” on page 432
Section 12.2.1, “USBCMD—USB Command Register” on
page 471
Section 12.2.2, “USBSTS—USB Status Register” on page 474
Section 12.2.3, “USBINTR—USB Interrupt Enable Register” on
page 475
Section 12.2.4, “FRNUM—Frame Number Register” on
page 475
Section 12.2.5, “FRBASEADD—Frame List Base Address
Register” on page 476
Section 12.2.6, “SOFMOD—Start of Frame Modify Register” on
page 476
Section 12.2.7, “PORTSC[0,1]—Port Status and Control
Register” on page 477
Section 12.2.7, “PORTSC[0,1]—Port Status and Control
Register” on page 477
Section 14.2.1, “HST_STS—Host Status Register (SMBUS—
D31:F3)” on page 522
Section 14.2.2, “HST_CNT—Host Control Register (SMBUS—
D31:F3)” on page 523
Section 14.2.3, “HST_CMD—Host Command Register
(SMBUS—D31:F3)” on page 525
Section 14.2.4, “XMIT_SLVA—Transmit Slave Address Register
(SMBUS—D31:F3)” on page 525
Section 14.2.5, “HST_D0—Host Data 0 Register (SMBUS—
D31:F3)” on page 525
Section 14.2.6, “HST_D1—Host Data 1 Register (SMBUS—
D31:F3)” on page 525
Section 14.2.7, “Host_BLOCK_DB—Host Block Data Byte
Register (SMBUS—D31:F3)” on page 526
on page 465
page 518
Datasheet Section and Location
Register Index
657