FW82801EB Intel, FW82801EB Datasheet - Page 313

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

8.1.26
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
DEVICE_HIDE—Secondary PCI Device Hiding Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
Power Well:
This register allows software to “hide” PCI devices (0 through 5) in terms of configuration space.
Specifically, when PCI devices (0
the PCI IDSEL pin does not assert. The ICH5 supports the hiding of six external devices
(0 through 5), which matches the number of PCI request/grant pairs, and the ability to hide the
integrated LAN device by masking out the configuration space decode of LAN controller. Writing
a 1 to this bit will not restrict the configuration cycle to the PCI bus. This differs from bits 0
through 5 in which the configuration cycle is restricted.
Hiding a PCI device can be useful for debugging, bug work-arounds, and system management
support. Devices should only be hidden during initialization before any configuration cycles are
run. This guarantees that the device is not in a semi-enable state.
15:9
Bit
7:6
8
5
4
3
2
1
0
Reserved
Hide Device 8 (HIDE_DEV8) — R/W. Same as bit 0 of this register, except for device 8 (AD24),
which is hardwired to the integrated LAN device.
This bit will not change the way the configuration cycle appears on PCI bus
Reserved
Hide Device 5 (HIDE_DEV5) — R/W. Same as bit 0 of this register, except for device 5 (AD21).
Hide Device 4 (HIDE_DEV4) — R/W. Same as bit 0 of this register, except for device 4 (AD20).
Hide Device 3 (HIDE_DEV3) — R/W. Same as bit 0 of this register, except for device 3 (AD19).
Hide Device 2 (HIDE_DEV2) — R/W. Same as bit 0 of this register, except for device 2 (AD18).
Hide Device 1 (HIDE_DEV1 ) — R/W. Same as bit 0 of this register, except for device 1 (AD17).
Hide Device 0 (HIDE_DEV0) — R/W.
0 = The PCI configuration cycles for this slot are not affected.
1 = Intel
for configuration cycles to that device. Since the device will not see its IDSEL go active, it will
not respond to PCI configuration cycles and the processor will think the device is not present.
AD16 is used as IDSEL for device 0.
®
ICH5 hides device 0 on the PCI bus. This is done by masking the IDSEL (keeping it low)
44
00h
00h
–
45h
–
5) are hidden, the configuration space is not accessible because
Hub Interface to PCI Bridge Registers (D30:F0)
Description
Attribute:
Size:
R/W
16 bits
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