FW82801EB Intel, FW82801EB Datasheet - Page 168

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
168
Note: Notes for previous two numbered lists.
If the system is in a G1 (S1–S4) state, the ICH5 sends a heartbeat message every 30–32 seconds. If
an event occurs prior to the system being shutdown, the ICH5 immediately sends an event message
with the next incremented sequence number. After the event message, the ICH5 resumes sending
heartbeat messages.
12. After step 1 (second timeout), if the user does a Power Button Override, the system goes to an
13. After step 12 (power button override), if the user presses the power button again, the system
14. If step 13 (power button press) is successful in waking the system, the ICH5 continues sending
15. If step 13 (power button press) is unsuccessful in waking the system, the ICH5 continues
16. After step 1 (second timeout), if a reset is attempted (using a button that pulses PWROK low
17. If step 16 (reset attempt) is successful, the BIOS is run. The ICH5 continues sending
18. If step 16 (reset attempt), is unsuccessful, the ICH5 continues sending heartbeats. The ICH5
1. Normally, the ICH5 does not send heartbeat messages while in the G0 state (except in the case
2. WARNING: It is important the BIOS clears the SECOND_TO_STS bit, as the alerts interfere
3. A system that has locked up and can not be restarted with power button press is assumed to
4. A spurious alert could occur in the following sequence:
S5 state. The ICH5 continues sending heartbeats at this point.
should wake to an S0 state and the processor should start executing the BIOS.
heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2)
sending heartbeats. The ICH5 does not attempt to reboot the system again until some external
intervention occurs (reset, power failure, etc.). (See note 3)
or via the message on the SMBus slave I/F), the ICH5 attempts to reset the system.
heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2)
does not attempt to reboot the system again without external intervention. (See note 3)
of a lockup). However, if a hardware event (or heartbeat) occurs just as the system is
transitioning into a G0 state, the hardware continues to send the message even though the
system is in a G0 state (and the status bits may indicate this).
These messages are sent via the SMBus. The ICH5 abides by the SMBus rules associated with
collision detection. It delays starting a message until the bus is idle, and detects collisions. If a
collision is detected the ICH5 waits until the bus is idle, and tries again.
with the LAN device driver from working properly. The alerts reset part of the LAN controller
and would prevent an OS’s device driver from sending or receiving some messages.
have broken hardware (bad power supply, short circuit on some bus, etc.), and is beyond
ICH5’s recovery mechanisms.
— The processor has initiated an alert using the SEND_NOW bit
— During the alert, the THRM#, INTRUDER# or GPI11 changes state
— The system then goes to a non-S0 state.
Intel
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82801EB ICH5 / 82801ER ICH5R Datasheet