FW82801EB Intel, FW82801EB Datasheet - Page 482

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
13.1.4
482
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
PCISTS—PCI Status Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
effect.
10:9
Bit
2:0
15
14
13
12
11
8
7
6
5
4
3
Detected Parity Error (DPE) — RO. Hardwired to 0.
Signaled System Error (SSE) — R/WC.
0 = No SERR# signaled by Intel
1 = This bit is set by the ICH5 when it signals SERR# (internally). The SER_EN bit (bit 8 of the
Received Master Abort (RMA) — R/WC.
0 = No master abort received by EHC on a memory access.
1 = This bit is set when EHC, as a master, receives a master abort status on a memory access.
Received Target Abort (RTA) — R/WC.
0 = No target abort received by EHC on memory access.
1 = This bit is set when EHC, as a master, receives a target abort status on a memory access. This
Signaled Target Abort (STA) — RO. This bit is used to indicate when the EHCI function responds to
a cycle with a target abort. There is no reason for this to happen, so this bit will be
hardwired to 0.
DEVSEL# Timing Status (DEVT_STS) — RO. This 2-bit field defines the timing for DEVSEL#
assertion.
Master Data Parity Error Detected (DPED) — R/WC.
0 = No data parity error detected on USB2.0 read completion packet.
1 = This bit is set by the ICH5 when a data parity error is detected on a USB 2.0 read completion
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
User Definable Features (UDF) — RO. Hardwired to 0.
66 MHz Capable (66 MHz _CAP) — RO. Hardwired to 0.
Capabilities List (CAP_LIST) — RO. Hardwired to 1 indicating that offset 34h contains a valid
capabilities pointer.
Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the input of the
enable/disable logic.
0 = This bit will be 0 when the interrupt is deasserted.
1 = This bit is a 1 when the interrupt is asserted.
The value reported in this bit is independent of the value in the Interrupt Enable bit.
Reserved
Command Register) must be 1 for this bit to be set.
This is treated as a Host Error and halts the DMA engines. This event can optionally generate
an SERR# by setting the SERR# Enable bit
is treated as a Host Error and halts the DMA engines. This event can optionally generate an
SERR# by setting the SERR# Enable bit
packet on the internal interface to the EHCI host controller (due to an equivalent data parity
error on hub interface) and bit 6 of the Command register is set to 1.
06
0290h
–
07h
®
ICH5.
Intel
Description
.
Attribute:
Size:
®
.
82801EB ICH5 / 82801ER ICH5R Datasheet
R/WC, RO
16 bits