FW82801EB Intel, FW82801EB Datasheet - Page 161

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.13.10.2
5.13.10.3
5.13.11
5.13.11.1
Intel
®
Table 70. PIC Reserved Bits Return Values
Table 71. Register Write Accesses in ALT Access Mode
82801EB ICH5 / 82801ER ICH5R Datasheet
PIC Reserved Bits
Many bits within the PIC are reserved, and must have certain values written in order for the PIC to
operate properly. Therefore, there is no need to return these values in ALT access mode. When
reading PIC registers from 20h and A0h, the reserved bits shall return the values listed in
Read Only Registers with Write Paths
in ALT Access Mode
The registers described in
restores these values after returning from a powered down state. These registers must be handled
special by software. When in normal mode, writing to the base address/count register also writes to
the current address/count register. Therefore, the base address/count must be written first, then the
part is put into ALT access mode and the current address/count register is written.
System Power Supplies, Planes, and Signals
Power Plane Control with SLP_S3#,
SLP_S4# and SLP_S5#
The SLP_S3# output signal can be used to cut power to the system core supply, since it only goes
active for the STR state (typically mapped to ACPI S3). Power must be maintained to the ICH5
resume well, and to any other circuits that need to generate Wake signals from the STR state.
Cutting power to the core may be done via the power supply, or by external FETs to the
motherboard. The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core
supply, as well as power to the system memory, since the context of the system is saved on the disk.
Cutting power to the memory may be done via the power supply, or by external FETs to the
motherboard.
I/O Address
PIC Reserved Bits
D0h
08h
OCW2(4:3)
OCW3(4:3)
ICW2(2:0)
ICW4(7:5)
ICW4(3:2)
OCW3(7)
OCW3(5)
ICW4(0)
DMA Status Register for channels 0–3.
DMA Status Register for channels 4–7.
Table 71
Register Write Value
Value Returned
Reflects bit 6
have write paths to them in ALT access mode. Software
000
000
00
00
01
0
0
Functional Description
Table
161
70.