FW82801EB Intel, FW82801EB Datasheet - Page 185

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.17
5.17.1
5.17.1.1
5.17.1.2
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: SATA interface transfer rates are independent of UDMA mode settings. SATA interface transfer
Standard ATA Emulation
SATA Host Controller (D31:F2)
The SATA function in the ICH5 has dual modes of operation to support different operating system
conditions. In the case of Native IDE enabled operating systems, the ICH5 has separate PCI
functions for serial and parallel ATA. To support legacy operating systems, there is only one PCI
function for both the serial and parallel ATA ports.
The MAP register,
enabled, all decode of I/O is done through the SATA registers. Device 31, Function 1
(IDE controller) is hidden by software writing to the Function Disable Register (D31, F0,
offset F2h, bit 1), and its configuration registers are not used. The SATA Capability Pointer
Register (offset 34h) will change to indicate that MSI is not supported in combined mode.
The ICH5 SATA controller features two sets of interface signals that can be independently enabled
or disabled (they cannot be tri-stated or driven low). Each interface is supported by an independent
DMA controller.
The ICH5 SATA controller interacts with an attached mass storage device through a register
interface that is equivalent to that presented by a traditional IDE host adapter. The host software
follows existing standards and conventions when accessing the register interface and follows
standard command protocol conventions.
rates will operate at the bus’s maximum speed, regardless of the UDMA mode reported by the
SATA device or the system BIOS.
Theory of Operation
The ICH5 contains a set of registers that shadow the contents of the legacy IDE registers. The
behavior of the Command and Control Block registers, PIO, and DMA data transfers, resets, and
interrupts are all emulated.
48-Bit LBA Operation
The SATA host controller supports 48-bit LBA through the host-to-device register FIS when
accesses are performed via writes to the task file. The SATA host controller will ensure that the
correct data is put into the correct byte of the host-to-device FIS.
There are special considerations when reading from the task file to support 48-bit LBA operation.
Software may need to read all 16-bits. Since the registers are only 8-bits wide and act as a FIFO, a
bit must be set in the device/control register, which is at offset 3F6h for primary and 376h for
secondary (or their native counterparts).
If software clears bit 7 of the control register before performing a read, the last item written will be
returned from the FIFO. If software sets bit 7 of the control register before performing a read, the
first item written will be returned from the FIFO.
Section
11.1.32, provides the ability to share PCI functions. When sharing is
Functional Description
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