FW82801EB Intel, FW82801EB Datasheet - Page 448

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

SATA Controller Registers (D31:F2)
11.1.25
11.1.26
f
448
PID—PCI Power Management Capability Identification
Register (SATA–D31:F2)
Address Offset:
Default Value:
PC—PCI Power Management Capabilities Register
(SATA–D31:F2)
Address Offset:
Default Value:
15:11
Bits
15:8
Bits
Bit
7:0
8:6
2:0
10
2
1
0
9
5
4
3
Secondary Drive 0 Base Clock (SCBO) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
Primary Drive 1 Base Clock (PCB1) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
Primary Drive 0 Base Clock (PCB0) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
Next Capability (NEXT) — RO. Indicates that this is the last item in the list.
Capability ID (CID) — RO. Indicates that this pointer is a PCI power management.
PME Support (PME_SUP) — RO. Hardwired to 0s to indicate PME# cannot be generated form the
SATA host controller. When in low power state, resume events are not allowed.
D2 Support (D2_SUP) — RO. Hardwired to 0. The D2 state is not supported
D1 Support (D1_SUP) — RO. Hardwired to 0. The D1 state is not supported
Auxiliary Current (AUX_CUR) — RO. Hardwired to 000 to indicate 375 mA maximum Suspend well
current required when in the D3 cold state.
Device Specific Initialization (DSI) — RO. Hardwired to 0 to indicate that no device-specific
initialization is required.
Reserved
PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that PCI clock is not required to generate
PME#.
Version (VER) — RO. Hardwired to 010 to indicates support for the PCI Power Management
Specification, Revision 1.1.
70
0001h
72
0002h
–
–
71h
73h
Description
Intel
Description
Description
Attribute:
Size:
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO
16 bits
RO
16 bits