FW82801EB Intel, FW82801EB Datasheet - Page 379

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.8.3
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0)
Offset Address:
Default Value:
Lockable:
NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC clock
Bit
7:6
5:4
3
2
1
0
period may not be detected by the ICH5.
SWSMI_RATE_SEL — R/W. This field indicates when the SWSMI timer will time out.
Valid values are:
00 = 1.5 ms ± 0.6 ms
01 = 16 ms ± 4 ms
10 = 32 ms ± 4 ms
11 = 64 ms ± 4 ms
SLP_S4# Minimum Assertion Width — R/W. This field indicates the minimum assertion width of
the SLP_S4# signal to guarantee that the DRAMs have been safely power-cycled.
Valid values are:
11 = 1 to 2 seconds
10 = 2 to 3 seconds
01 = 3 to 4 seconds
00 = 4 to 5 seconds
This value is used in two ways:
RTCRST# forces this field to the conservative default state (00b).
SLP_S4# Assertion Stretch Enable — RW.
1 = the SLP_S4# signal minimally assert for the time specified in bits 5:4 of this register.
0 = the SLP_S4# minimum assertion time is 1 to 2 RTCCLK.
This bit is cleared by RTCRST#.
RTC_PWR_STSRTC Power Status (RTC_PWR_STS) — R/W. This bit is set when RTCRST#
indicates a weak or missing battery. The bit is not cleared by any type of reset. When the system
boots, BIOS can detect that the FREQ_STRAP register contents are 1111 (the default when
RTCRST# has been low). If this bit is also set, then BIOS knows the RTC battery had been
removed. In that case, BIOS should take steps to reprogram the FREQ_STRAP register with the
correct value, and then reboot the system.
Power Failure (PWR_FLR) — R/WC. This bit is in the RTC well, and is not cleared by any type of
reset except RTCRST#.
0 = Indicates that the trickle current has not failed since the last time the bit was cleared. Software
1 = Indicates that the trickle current (from the main battery or trickle supply) was removed or failed.
NOTE: Clearing CMOS in an ICH-based platform can be done by using a jumper on RTCRST# or
AFTERG3_EN — R/W. This bit determines what state to go to when power is re-applied after a
power failure (G3 state). This bit is in the RTC well and is not cleared by any type of reset except
writes to CF9h or RTCRST#.
0 = System will return to S0 state (boot) after power is re-applied.
1 = System will return to the S5 state (except if it was in S4, in which case it will return to S4). In the
1. If the SLP_S4# assertion width is ever shorter than this time, a status bit is set for BIOS to read
2. If enabled by bit 3 in this register, the hardware will prevent the SLP_S4# signal from deasserting
when S0 is entered.
within this minimum time period after asserting.
clears this bit by writing a 1 to it.
S5 state, the only enabled wake event is the Power Button or any enabled wake event that was
preserved through the power failure.
GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by
using a jumper to pull VccRTC low.
A4h
00h
No
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Usage:
Power Well:
R/W, R/WC
8-bit
ACPI, Legacy
RTC
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