FW82801EB Intel, FW82801EB Datasheet - Page 476

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

UHCI Controllers Registers
12.2.5
12.2.6
476
FRBASEADD—Frame List Base Address Register
I/O Offset:
Default Value:
This 32-bit register contains the beginning address of the Frame List in the system memory. HCD
loads this register prior to starting the schedule execution by the host controller. When written, only
the upper 20 bits are used. The lower 12 bits are written as 0s (4-KB alignment). The contents of
this register are combined with the frame number counter to enable the host controller to step
through the frame list in sequence. The two least significant bits are always 00. This requires
DWord alignment for all list entries. This configuration supports 1024 frame list entries.
SOFMOD—Start of Frame Modify Register
I/O Offset:
Default Value:
This 1-byte register is used to modify the value used in the generation of SOF timing on the USB.
Only the seven, least significant bits are used. When a new value is written into these seven bits,
the SOF timing of the next frame will be adjusted. This feature can be used to adjust out any offset
from the clock source that generates the clock that drives the SOF counter. This register can also be
used to maintain real time synchronization with the rest of the system so that all devices have the
same sense of real time. Using this register, the frame length can be adjusted across the full range
required by the Universal Serial Bus Revision 2.0 Specification. Its initial programmed value is
system dependent based on the accuracy of hardware USB clock and is initialized by system BIOS.
It may be reprogrammed by USB system software at any time. Its value will take effect from the
beginning of the next frame. This register is reset upon a Host Controller Reset or Global Reset.
Software must maintain a copy of its value for reprogramming if necessary.
31:12
Bit
6:0
11:0
Bit
7
Reserved
SOF Timing Value — R/W. Guidelines for the modification of frame time are contained in Chapter 7
of the Universal Serial Bus Revision 2.0 Specification. The SOF cycle time (number of SOF counter
clock periods to generate a SOF frame length) is equal to 11936 + value in this field. The default value
is decimal 64 which gives a SOF cycle time of 12000. For a 12 MHz SOF counter clock input, this
produces a 1 ms Frame period. The following table indicates what SOF Timing Value to program into
this field for a certain frame period.
Base Address — R/W. These bits correspond to memory address signals [31:12], respectively.
Reserved
Frame Length
(# 12 MHz Clocks) SOF Reg. Value
11936
11937
.
.
11999
12000
12001
.
.
12062
12063
(decimal)
Base + (08
Undefined
Base + (0Ch)
40h
(decimal)
0
1
.
.
63
64
65
.
.
126
127
–
0Bh)
Description
Intel
Description
Attribute:
Size:
®
Attribute:
Size:
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
32 bits
R/W
8 bits