FW82801EB Intel, FW82801EB Datasheet - Page 381
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FW82801EB
Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet
1.FW82801EB.pdf
(671 pages)
Specifications of FW82801EB
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9.8.7
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
GPI_ROUT—GPI Routing Control Register
(PM—D31:F0)
Offset Address:
Default Value:
Lockable:
NOTE: GPIOs that are not implemented will not have the corresponding bits implemented in this register.
31:30
Bit
5:4
3:2
1:0
GPI15 Route — R/W. See bits 1:0 for description.
GPI2 Route — R/W. See bits 1:0 for description.
GPI1 Route — R/W. See bits 1:0 for description.
GPI0 Route — R/W. GPIO[15:0] can be routed to cause an SMI or SCI when the GPI[n]_STS bit is
set. If the GPIO is not set to an input, this field has no effect.
If the system is in an S1–S5 state and if the GPE0_EN bit is also set, then the GPI can cause a
Wake event, even if the GPI is NOT routed to cause an SMI# or SCI.
00 = No effect.
01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
10 = SCI (if corresponding GPE0_EN bit is also set)
11 = Reserved
B8h
0000h
No
–
BBh
Same pattern for GPI14 through GPI3
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
R/W
32-bit
Resume
381
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