FW82801EB Intel, FW82801EB Datasheet - Page 504

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
13.2.7
504
USB2.0_INTR—USB 2.0 Interrupt Enable Register
Offset:
Default Value:
This register enables and disables reporting of the corresponding interrupt to the software. When a
bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt
sources that are disabled in this register still appear in the USB2.0_STS Register to allow the
software to poll for events. Each interrupt enable bit description indicates whether it is dependent
on the interrupt threshold mechanism (see Section 4 of the Enhanced Host Controller Interface
Specification for Universal Serial Bus, Revision 1.0, or not.
31:6
Bit
5
4
3
2
1
0
Reserved. These bits are reserved and should be 0 when writing this register.
Interrupt on Async Advance Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1, and the Interrupt on Async Advance bit in the USB2.0_STS
Host System Error Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1, and the Host System Error Status bit in the USB2.0_STS register
Frame List Rollover Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1, and the Frame List Rollover bit in the USB2.0_STS register is a 1,
Port Change Interrupt Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1, and the Port Change Detect bit in the USB2.0_STS register is a 1,
USB Error Interrupt Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1, and the USBERRINT bit in the USB2.0_STS register is a 1, the
USB Interrupt Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1, and the USBINT bit in the USB2.0_STS register is a 1, the host
register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the Interrupt on Async Advance bit.
is a 1, the host controller will issue an interrupt. The interrupt is acknowledged by software
clearing the Host System Error bit.
the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the
Frame List Rollover bit.
the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the
Port Change Detect bit.
host controller will issue an interrupt at the next interrupt threshold. The interrupt is
acknowledged by software by clearing the USBERRINT bit in the USB2.0_STS register.
controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by
software by clearing the USBINT bit in the USB2.0_STS register.
CAPLENGTH + 08
00000000h
–
0Bh
Intel
Description
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
32 bits