FW82801EB Intel, FW82801EB Datasheet - Page 642

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Register Index
642
Table 204. Intel
TCO Control
GPIO Base Address
Register
GPIO Control Register
PIRQ[A:D] Routing Control
Serial IRQ Control Register
PIRQ[E:H] Routing Control
Device 31 Error Config
Register
Device 31 Error Status
Register
PCI DMA Configuration
Registers
General Power
Management Configuration
1
General Power
Management Configuration
2
General Power
Management Configuration
3
Stop Clock Delay Register
GPI_ROUT
I/O Monitor [4:7] Trap
Range Registers
I/O Monitor [4:7] Trap Mask
Register
General Control
General Status
Backed Up Control
Real Time Clock
Configuration
LPC COM Port Decode
Ranges
LPC FDD & LPT Decode
Ranges
Forwarding Enable
®
I/O Monitor Trap
Register Name
ICH5 PCI Configuration Registers (Sheet 4 of 11)
Register
C4h, C6h,
C8h, CAh
D0h – D3h
B8 – BBh
58 – 5Bh
60 – 63h
68 – 6Bh
90 – 91h
Offset
CCh
5Ch
8Ah
A0h
A2h
A4h
A8h
C0h
D4h
D5h
D8h
E0h
E1h
54h
64h
88h
Section 9.1.13, “TCO_CNTL — TCO Control Register (LPC I/F
— D31:F0)” on page 324
Section 9.1.14, “GPIO_BASE—GPIO Base Address Register
(LPC I/F—D31:F0)” on page 325
Section 9.1.15, “GPIO_CNTL—GPIO Control Register (LPC I/
F—D31:F0)” on page 325
Section 9.1.16, “PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing
Control Register (LPC I/F—D31:F0)” on page 326
Section 9.1.17, “SIRQ_CNTL—Serial IRQ Control Register
(LPC I/F—D31:F0)” on page 327
Section 9.1.8, “BCC—Base Class Code Register (LPC I/F—
D31:F0)” on page 321
Section 9.1.19, “D31_ERR_CFG—Device 31 Error
Configuration Register (LPC I/F—D31:F0)” on page 328
Section 9.1.20, “D31_ERR_STS—Device 31 Error Status
Register (LPC I/F—D31:F0)” on page 329
Section 9.1.21, “PCI_DMA_CFG—PCI DMA Configuration
Register (LPC I/F—D31:F0)” on page 329
Section 9.8.1, “GEN_PMCON_1—General PM Configuration 1
Register (PM—D31:F0)” on page 377
Section 9.8.2, “GEN_PMCON_2—General PM Configuration 2
Register (PM—D31:F0)” on page 378
Section 9.8.3, “GEN_PMCON_3—General PM Configuration 3
Register (PM—D31:F0)” on page 379
Section 9.8.4, “STPCLK_DEL—Stop Clock Delay Register
(PM—D31:F0)” on page 380
Section 9.8.7, “GPI_ROUT—GPI Routing Control Register
(PM—D31:F0)” on page 381
Section 9.8.8, “TRP_FWD_EN—IO Monitor Trap Forwarding
Enable Register (PM—D31:F0)” on page 382
Section 9.8.9, “MON[n]_TRP_RNG—I/O Monitor [4:7] Trap
Range Register for Devices 4–7 (PM—D31:F0)” on page 383
Section 9.8.10, “MON_TRP_MSK—I/O Monitor Trap Range
Mask Register for Devices 4–7 (PM—D31:F0)” on page 383
Section 9.1.22, “GEN_CNTL — General Control Register (LPC
I/F — D31:F0)” on page 330
Section 9.1.23, “GEN_STA—General Status Register (LPC I/F—
D31:F0)” on page 332
Section 9.1.24, “BACK_CNTL—Backed Up Control Register
(LPC I/F—D31:F0)” on page 333
Section 9.1.25, “RTC_CONF—Real Time Clock Configuration
Register (LPC I/F—D31:F0)” on page 334
Section 9.1.26, “COM_DEC—LPC I/F Communication Port
Decode Ranges Register (LPC I/F—D31:F0)” on page 335
Section 9.1.27, “LPCFDD_DEC—LPC I/F FDD and LPT Decode
Ranges Register (LPC I/F—D31:F0)” on page 335
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Datasheet Section and Location