FW82801EB Intel, FW82801EB Datasheet - Page 284

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LAN Controller Registers (B1:D8:F0)
7.1.21
7.1.22
284
NXT_PTR — Next Item Pointer Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
PM_CAP — Power Management Capabilities Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
15:11
Bit
7:0
8:6
2:0
Bit
10
9
5
4
3
Next Item Pointer (NXT_PTR)
last item in the capabilities list.
PME Support (PME_SUP) — RO. Hardwired to 11111b. This 5-bit field indicates the power states in
which the LAN controller may assert PME#. The LAN controller supports wake-up in all power
states.
D2 Support (D2_SUP) — RO. Hardwired to 1 to indicate that the LAN controller supports the D2
power state.
D1 Support (D1_SUP) — RO. Hardwired to 1 to indicate that the LAN controller supports the D1
power state.
Auxiliary Current (AUX_CUR) — RO. Hardwired to 000b to indicate that the LAN controller
implements the Data registers. The auxiliary power consumption is the same as the current
consumption reported in the D3 state in the Data register.
Device Specific Initialization (DSI) — RO. Hardwired to 1 to indicate that special initialization of this
function is required (beyond the standard PCI configuration header) before the generic class device
driver is able to use it. DSI is required for the LAN controller after D3-to-D0 reset.
Reserved
PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that the LAN controller does not require a
clock to generate a power management event.
Version (VER) — RO. Hardwired to 010b to indicate that the LAN controller complies with of the PCI
Power Management Specification, Revision 1.1.
DDh
00h
DE
FE21h
–
DFh
—
RO. Hardwired to 00b to indicate that power management is the
Description
Intel
Description
Attribute:
Size:
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO
8 bits
RO
16 bits