FW82801EB Intel, FW82801EB Datasheet - Page 263

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.22.3.1
Intel
®
Figure 29. SDIN Wake Signaling
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: Before entering any low-power mode where the link interface to the codec is expected to be
AC_BIT_CLK and AC_SDIN transition low immediately after a write to the Powerdown Register
(26h) with PR4 enabled. When the AC ’97 controller driver is at the point where it is ready to
program the AC-link into its low-power mode, slots 1 and 2 are assumed to be the only valid
stream in the audio output frame.
The AC ’97 controller also drives AC_SYNC, and AC_SDOUT low after programming AC ’97 to
this low power, halted mode
Once the codec has been instructed to halt, AC_BIT_CLK, a special wake up protocol must be
used to bring the AC-link to the active mode since normal output and input frames can not be
communicated in the absence of AC_BIT_CLK. Once in a low-power mode, the ICH5 provides
three methods for waking up the AC-link; external wake event, cold reset and warm reset.
powered down while the rest of the system is awake, the software must set the “Shut Off” bit in the
control register.
External Wake Event
Codecs can signal the controller to wake the AC-link, and wake the system using AC_SDIN.
The minimum AC_SDIN wake up pulse width is 1 us. The rising edge of AC_SDIN0, AC_SDIN1
or AC_SDIN2 causes the ICH5 to sequence through an AC-link warm reset and set the AC97_STS
bit in the GPE0_STS register to wake the system. The primary codec must wait to sample
AC_SYNC high and low before restarting AC_BIT_CLK as diagrammed in
that signaled the wake event must keep its AC_SDIN high until it has sampled AC_SYNC having
gone high, and then low.
The AC-link protocol provides for a cold reset and a warm reset. The type of reset used depends on
the system’s current power down state. Unless a cold or register reset (a write to the Reset register
in the codec) is performed, wherein the AC ’97 codec registers are initialized to their default
values, registers are required to keep state during all power down modes.
Once powered down, activation of the AC-link via re-assertion of the AC_SYNC signal must not
occur for a minimum of four audio frame times following the frame in which the power down was
triggered. When AC-link powers up, it indicates readiness via the codec ready bit.
BIT_CLK
SDOUT
SDIN
SYNC
prev. frame
prev. frame
slot 12
slot 12
TAG
TAG
Power Down
Write to
Frame
0x20
Data
PR4
Sleep State
Wake Event
Functional Description
Figure
TAG
TAG
New Audio
Frame
Slot 1
Slot 1
27. The codec
Slot 2
Slot 2
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