FW82801EB Intel, FW82801EB Datasheet - Page 651

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 205. Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
Aliased at 20h – 21h
Aliased at 20h – 21h
Aliased at 20h – 21h
Aliased at 20h – 21h
Aliased at 20h – 21h
Aliased at 20h – 21h
Counter 0 Interval Time
Status Byte Format
Counter 0 Counter Access
Port Register
Counter 1 Interval Time
Status Byte Format
Counter 1 Counter Access
Port Register
Counter 2 Interval Time
Status Byte Format
Counter 2 Counter Access
Port Register
Timer Control Word
Register
Timer Control Word
Register Read Back
Counter Latch Command
Aliased at 40h – 43h
NMI Status and Control
Register
NMI Enable Register
Real-Time Clock (Standard
RAM) Index Register
Real-Time Clock (Standard
RAM) Target Register
Extended RAM Index
Register
Extended RAM Target
Register
Aliased at 70h – 71h
Aliased at 72h – 73h or
70h – 71h
Channel 2 DMA Memory
Low Page Register
®
Register Name
ICH5 Fixed I/O Registers (Sheet 2 of 5)
2Ch – 2Dh
3Ch – 3Dh
24h – 25h
30h – 31h
34h – 35h
38h – 39h
50h – 53h
74h – 75h
76h – 77h
Port
40h
41h
42h
43h
61h
70h
70h
71h
72h
73h
81h
Section 9.3.2, “SBYTE_FMT—Interval Timer Status Byte Format
Register (LPC I/F—D31:F0)” on page 354
Section 9.3.3, “Counter Access Ports Register (LPC I/F—
D31:F0)” on page 355
Section 9.3.2, “SBYTE_FMT—Interval Timer Status Byte Format
Register (LPC I/F—D31:F0)” on page 354
Section 9.3.3, “Counter Access Ports Register (LPC I/F—
D31:F0)” on page 355
Section 9.3.2, “SBYTE_FMT—Interval Timer Status Byte Format
Register (LPC I/F—D31:F0)” on page 354
Section 9.3.3, “Counter Access Ports Register (LPC I/F—
D31:F0)” on page 355
Section 9.3.1, “TCW—Timer Control Word Register (LPC I/F—
D31:F0)” on page 352
Section 9.3.1.1, “RDBK_CMD—Read Back Command (LPC I/
F—D31:F0)” on page 353
Section 9.3.1.2, “LTCH_CMD—Counter Latch Command (LPC I/
F—D31:F0)” on page 353
Section 9.7.1, “NMI_SC—NMI Status and Control Register (LPC
I/F—D31:F0)” on page 373
Section 9.7.2, “NMI_EN—NMI Enable (and Real Time Clock
Index) Register (LPC I/F—D31:F0)” on page 374
Section 147, “RTC (Standard) RAM Bank (LPC I/F—D31:F0)” on
page 369
Section 9.7.2, “NMI_EN—NMI Enable (and Real Time Clock
Index) Register (LPC I/F—D31:F0)” on page 374
Section 147, “RTC (Standard) RAM Bank (LPC I/F—D31:F0)” on
page 369
Aliased if U128E bit in RTC Configuration Register is enabled
Section 9.1.24, “BACK_CNTL—Backed Up Control Register
(LPC I/F—D31:F0)” on page 333
Aliased to 70h – 71h if U128E bit in RTC Configuration Register is
enabled
Section 9.1.24, “BACK_CNTL—Backed Up Control Register
(LPC I/F—D31:F0)” on page 333
Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page
Registers (LPC I/F—D31:F0)” on page 346
Datasheet Section and Location
Register Index
651