FW82801EB Intel, FW82801EB Datasheet - Page 83

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.1.6
5.1.6.1
5.1.6.2
Intel
®
Table 31. Type 0 Configuration Cycle Device Number Translation
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: Configuration writes to internal devices, when the devices are disabled, are illegal and may cause
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to contain up to
eight functions with each function containing up to 256, 8-bit configuration registers. The PCI
Local Bus Specification, Revision 2.3 defines two bus cycles to access the PCI configuration space:
Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the
processor. Configuration space is supported by a mapping mechanism implemented within the
ICH5. The PCI Local Bus Specification, Revision 2.3 defines two mechanisms to access
configuration space, Mechanism 1 and Mechanism 2. The ICH5 only supports Mechanism 1.
Configuration cycles for PCI Bus 0 devices 2 through 31, and for PCI Bus numbers greater than 0
are sent towards the ICH5 from the host controller. The ICH5 compares the non-zero Bus Number
with the Secondary Bus Number and Subordinate Bus number registers of its PCI-to-PCI bridge to
determine if the configuration cycle is meant for primary PCI or a downstream PCI bus.
undefined results.
Type 0 to Type 0 Forwarding
When a Type 0 configuration cycle is received on hub interface to any function other than EHCI or
AC ’97, the ICH5 forwards these cycles to PCI and then reclaims them. The ICH5 uses address bits
AD[15:13] to communicate the ICH5 device numbers in Type 0 configuration cycles. If the Type 0
cycle on hub interface specifies any device number other than 29, 30 or 31, the ICH5 will not set
any address bits in the range AD[31:11] during the corresponding transaction on PCI.
shows the device number translation.
The ICH5 logic generates single DWord configuration read and write cycles on the PCI bus. The
ICH5 generates a Type 0 configuration cycle for configurations to the bus number matching the
PCI bus. Type 1 configuration cycles are converted to Type 0 cycles in this case. If the cycle is
targeting a device behind an external bridge, the ICH5 runs a Type 1 cycle on the PCI bus.
Type 1 to Type 0 Conversion
When the bus number for the Type 1 configuration cycle matches the PCI (Secondary) bus number,
the ICH5 converts the address as follows:
1. For device numbers 0 through 15, only 1 bit of the PCI address [31:16] is set. If the device
2. The ICH5 always drives 0s on bits AD[15:11] when converting Type 1 configurations cycles
3. Address bits [10:1] are also be passed unchanged to PCI.
4. Address bit 0 is changed to 0.
Device # in Hub Interface
number is 0, AD16 is set; if the device number is 1, AD17 is set; etc.
to Type 0 configuration cycles on PCI.
Type 0 Cycle
0 through 28
29
30
31
AD[31:11] during Address Phase of
0000000000000000_00000b
0000000000000000_00100b
0000000000000000_01000b
0000000000000000_10000b
Type 0 Cycle on PCI
Functional Description
Table 31
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