FW82801EB Intel, FW82801EB Datasheet - Page 291

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

7.2.3
7.2.4
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
SCB_GENPNT—System Control Block General Pointer
Register (LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
PORT—PORT Interface Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
The PORT interface allows the processor to reset the ICH5’s internal LAN controller, or perform
an internal self test. The PORT DWord may be written as a 32-bit entity, two 16-bit entities, or four
8-bit entities. The LAN controller will only accept the command after the high byte (offset 0Bh) is
written; therefore, the high byte must be written last.
15:0
31:4
Bit
Bit
3:0
SCB General Pointer — R/W. The SCB General Pointer register is programmed by software to
point to various data structures in main memory depending on the current SCB Command word.
Pointer Field (PORT_PTR) — R/W (special). A 16-byte aligned address must be written to this field
when issuing a Self-Test command to the PORT interface.The results of the Self Test will be written
to the address specified by this field.
PORT Function Selection (PORT_FUNC) — R/W (special). Valid values are listed below. All other
values are reserved.
0000 = PORT Software Reset: Completely resets the LAN controller (all CSR and PCI registers).
0001 = Self Test: The Self-Test begins by issuing an internal Selective Reset followed by a general
0010 = Selective Reset: Sets the CU and RU to the Idle state, but otherwise maintains the current
This command should not be used when the device is active. If a PORT Software Reset is
desired, software should do a Selective Reset (described below), wait for the PORT register
to be cleared (completion of the Selective Reset), and then issue the PORT Software Reset
command. Software should wait approximately 10 µs after issuing this command before
attempting to access the LAN controller’s registers again.
internal self-test of the LAN controller. The results of the self-test are written to memory at the
address specified in the Pointer field of this register. The format of the self-test result is
shown in
controller will execute a full internal reset and will re-initialize to the default configuration.
Self-Test does not generate an interrupt of similar indicator to the host processor upon
completion.
configuration parameters (RU and CU Base, HDSSize, Error Counters, Configure
information and Individual/Multicast Addresses are preserved). Software should wait
approximately 10 µs after issuing this command before attempting to access the LAN
controller’s registers again.
04
0000 0000h
08
0000 0000h
–
–
07h
0Bh
Table
138. After completing the self-test and writing the results to memory, the LAN
Description
Description
Attribute:
Size:
Attribute:
Size:
LAN Controller Registers (B1:D8:F0)
R/W
32 bits
R/W (special)
32 bits
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