SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 101

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Host Interface (HI08)
The host interface (HI08) is a byte-wide, full-duplex, double-buffered parallel port that can
connect directly to the data bus of a host processor. The HI08 supports a variety of buses and
provides glueless connection with a number of industry-standard microcomputers,
microprocessors, and DSPs. The HI08 signals not used to interface to the host can be configured
as GPIO signals, up to a total of 16.
6.1 Features
The HI08 host is a slave device that operates asynchronously to the DSP core and host clocks.
Thus, the HI08 peripheral has a host processor interface and a DSP core interface. This section
lists the features of the host processor and DSP core interfaces.
6.1.1 DSP Core Interface
6.1.2 Host Processor Interface
Freescale Semiconductor
Mapping: Registers are directly mapped into eight internal X data memory locations.
Data word: DSP56303 24-bit (native) data words are supported, as are 8-bit and 16-bit
words.
Handshaking protocols:
— Software polled
— Interrupt driven
— Core DMA accesses
Instructions:
— Memory-mapped registers allow the standard MOVE instruction to transfer data
— A special MOVEP instruction for I/O service capability using fast interrupts.
— Bit addressing instructions (for example, BCHG, BCLR, BSET, BTST, JCLR, JSCLR,
Sixteen signals support non-multiplexed or multiplexed buses:
—
—
—
—
between the DSP56303 and external hosts.
JSET, JSSET) simplify I/O service routines.
H[0–7]
HAS
HA8
HA9
/
/
/
HA1
HA2
HA0
/
HAD[0–7]
host address line (
host address line (
address strobe (
host data bus (
HAS
DSP56303 User’s Manual, Rev. 2
HA8
HA9
) or host address line (
H[0–7]
) or host address line (
) or host address line (
) or host multiplexed address/data bus (
HA0
HA1
HA2
)
)
)
HAD[0–7]
6
)
6-1