SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 27

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.1 Power
2.2 Ground
Freescale Semiconductor
V
V
V
V
V
V
V
Note:
GND
GND
GND
CCP
CCQ
CCA
CCD
CCC
CCH
CCS
Power Name
Ground Name
P
P1
Q
(4)
(2)
(4)
(4)
(2)
(4)
These designations are package-dependent. Some packages connect all V
internally. On those packages, all power input except V
in this table are minimum values; the total V
PLL Power
V
should be provided with an extremely low impedance path to the V
Quiet Power
An isolated power for the internal processing logic. This input must be tied externally to all other chip
power inputs, except for V
Address Bus Power
An isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other
chip power inputs, except for V
Data Bus Power
An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other
chip power inputs, except for V
Bus Control Power
An isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power
inputs, except for V
Host Power
An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power inputs,
except for V
ESSI, SCI, and Timer Power
An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other
chip power inputs, except for V
PLL Ground
Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground. V
to the chip package.
PLL Ground 1
Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground.
Quiet Ground
An isolated ground for the internal processing logic. This connection must be tied externally to all other
chip ground connections, except GND
decoupling capacitors.
CC
dedicated for use with Phase Lock Loop (PLL). The voltage should be well-regulated and the input
CCP
. The user must provide adequate external decoupling capacitors.
CCP
CCP
should be bypassed to GND
. The user must provide adequate external decoupling capacitors.
DSP56303 User’s Manual, Rev. 2
Table 2-2. Power Inputs
CCP
Table 2-3. Grounds
. The user must provide adequate external decoupling capacitors.
CCP
CCP
CCP
CC
. The user must provide adequate external decoupling capacitors.
. The user must provide adequate external decoupling capacitors.
. The user must provide adequate external decoupling capacitors.
connections are package-dependent.
P
and GND
CCP
Description
Description
are labeled V
P1
P
by a 0.47 µF capacitor located as close as possible
. The user must provide adequate external
CC
CC
. The numbers of connections indicated
CC
inputs except V
power rail.
CCP
to each other
Power
2-3