SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 188

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Communication Interface (SCI)
8.6.4.1 SCI Receive Register (SRX)
Data bits received on the
complete word is received, the data portion of the word is transferred to the byte-wide SRX. This
process converts serial data to parallel data and provides double buffering. Double buffering
promotes flexibility and increased throughput since the programmer can save (and process) the
previous word while the current word is being received.
The SRX can be read at three locations as SRXL, SRXM, and SRXH. When SRXL is read, the
contents of the SRX are placed in the lower byte of the data bus and the remaining bits on the
data bus are read as zeros. Similarly, when SRXM is read, the contents of SRX are placed into the
middle byte of the bus, and when SRXH is read, the contents of SRX are placed into the high
byte with the remaining bits are read as 0s. This way of mapping SRX efficiently packs three
bytes into one 24-bit word by ORing three data bytes read from the three addresses.
The SCR WDS0, WDS1, and WDS2 control bits define the length and format of the serial word.
The SCR receive clock mode (RCM) defines the clock source.
8-20
23
23
23
SCI Transmit Data Shift Register
Note: SRX is the same register decoded at three different addresses.
Note: Bytes are masked on the fly.
STX is the same register decoded at four different addresses.
SRX
RXD
STX
16
16
16
Figure 8-7. SCI Programming Model—Data Registers
15
15
15
RXD
SRX
STX
signal are shifted into the SCI receive shift register. When a
DSP56303 User’s Manual, Rev. 2
(b) Transmit Data Register
8
8
8
(a) Receive Data Register
7
7
7
SCI Receive Data Shift Register
STXA
SRX
STX
0
0
0
SCI Transmit Data Address Register (Write Only)
SCI Receive Data Register High (Read Only)
SCI Receive Data Register Middle (Read Only)
SCI Receive Data Register Low (Read Only)
SCI Transmit Data Register High (Write Only)
SCI Transmit Data Register Middle (Write Only)
SCI Transmit Data Register Low (Write Only)
TXD
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