SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 107

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

These interrupts are maskable via the Host Receive Interrupt Enable bit (HCR[0] = HRIE), the
Host Transmit Interrupt Enable bit (HCR[1] = HTIE), and the Host Command Interrupt Enable
bit (HCR[2] = HCIE), respectively. Receive Data Full and Transmit Data Empty interrupts move
data to/from the HTX and HRX data registers. The DSP interrupt service routine must read or
write the appropriate HI08 data register (HRX or HTX) to clear the interrupt condition.
Host commands allow the host to issue command requests to the DSP by selecting any of 128
DSP interrupt routines for execution. For example, the host may issue a command via the HI08
that sets up and enables a DMA transfer. The DSP56303 processor has reserved interrupt vector
addresses for application-specific service routines. However, this flexibility is independent of the
data transfer mechanisms in the HI08 and allows the host to force execution of any interrupt
handler (for example, SSI, SCI, IRQx, and so on).
To enable Host Command interrupts, the HCR[2] = HCIE bit is set on the DSP side. The host
then uses the Command Vector Register (CVR) to start an interrupt routine. The host sets the
Host Command bit (CVR[7] = HC) to request the command interrupt and the seven Host Vector
bits CVR[6–0] = HV[6–0] to select the interrupt address to be used. When the DSP core
recognizes the host command interrupt, the address of the interrupt taken is 2xHV. For host
command interrupts, the interrupt acknowledge from the DSP56303 program controller clears the
pending interrupt condition.
Freescale Semiconductor
Host command
Transmit data register empty
Receive data register full
X:HCR
X:HSR
15
15
Figure 6-2. HI08 Core Interrupt Operation
HF3
HF1
DSP56303 User’s Manual, Rev. 2
HF2
HF0
HCIE HTIE HRIE HCR
HCP HTDE HRDF HSR
Enable
Status
0
0
DSP Core Interrupts
Receive Data Full
Transmit Data Empty
Host Command
Operation
6-7