SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 205

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.2.2 Measurement Input Period (Mode 5)
In Mode 5, the timer counts the period between the reception of signal edges of the same polarity
across the
between consecutive low-to-high (0 to 1) transitions of
(1 to 0) transitions of
cleared, low-to-high signal transitions are selected. After the first appropriate transition occurs on
the
same polarity that occurs on
TCSR[TCIE] bit is set. The contents of the counter load into the TCR. The TCR then contains the
value of the time that elapsed between the two signal transitions on the
second signal transition, if the TCSR[TRM] bit is set, the TCSR[TE] bit is set to clear the counter
and enable the timer. The counter is repeatedly loaded and incremented until the timer is
disabled. If the TCSR[TRM] bit is cleared, the counter continues to increment until it overflows.
Freescale Semiconductor
TC3
0
TIO
Mode 4 (internal clock): TRM = 1
TCF (Compare Interrupt if TCIE = 1)
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter
TCR
TIO pin
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
stops the counter and loads TCR with the count.
input signal, the counter is loaded with the TLR value. On the next signal transition of the
TC2
TIO
Bit Settings
1
signal. The value of the INV bit determines whether the period is measured
TC1
0
Figure 9-12. Pulse Width Measurement Mode, TRM = 0
TIO
. If INV is set, high-to-low signal transitions are selected. If INV is
TC0
N
1
TIO
0
, TCSR[TCF] is set, and a compare interrupt is generated if the
Mode
first event
DSP56303 User’s Manual, Rev. 2
5
width being measured
N
Input period
Name
N + 1
Mode Characteristics
TIO
or between consecutive high-to-low
Measurement
Function
M
M
TIO
signal. After the
Interrupt Service
reads TCR for
accumulated width
of M - N clock periods.
Next 0-to-1 edge
on TIO starts
counter from current
count and process
repeats. Overflow
may occur (TOF = 1).
Input
TIO
N + 1
Operating Modes
Internal
Clock
9-13